RTL2PD Design Engineer (ASIC)

Inabia Software & Consulting Inc.; San Francisco (CA); On-site; USD 103,000 - 110,000; Full time

Job summary

Arrow Electronics is seeking an experienced RTL2PD Design Engineer for onsite work in the Bay Area, CA. The role focuses on RTL synthesis, constraint writing, validation, and STA to drive RTL2PD transitions for ASIC projects.

Required are 8–12 years of hands-on RTL synthesis expertise, proficiency with Design Compiler, PrimeTime, Tempus and Genus, and experience with 16nm/7nm nodes. C2C engagements are allowed, and H1B transfers are restricted.

Qualifications

• 8–12 years of hands-on RTL Synthesis experience.
• Experience with EDA tools: Design Compiler, PrimeTime, Tempus, Genus.
• Experience with multi-node designs (16nm, 7nm).
• MUST HAVE RTL Synthesis, Constraint writing, validation, STA.

Responsibilities

• RTL Synthesis, Constraint writing, validation, Static timing Analysis.
• Write/modify scripts for RTL synthesis, SDC creation, STA.
• Debug synthesis issues and STA.
• Generate clean netlist.

Skills

RTL Synthesis

Constraint writing

Static timing analysis

Scripting

RTL2PD

Tools

Design Compiler

PrimeTime

Tempus

Genus

Job description

Hello,

Job Title : RTL2PD Design Engineer / RTL2PD Design Engineer (ASIC)

Client: Arrow Electronics

Experience Required: 8–12 years of hands-on experience

Pay Rate - $75/hr on W2 and $80/hr on C2C

Work Location:Bay Area, CA (Onsite)

Visa: All visa, except H1B transfer

C2C engagements are allowed.

RTL to Physical Design (RTL2PD) stage experience

MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis

What candidate will Be Doing:

RTL Synthesis, Constraint writing, validation, Static timing Analysis

Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA

Debug synthesis issues and STA

Generate clean netlist.

What we are looking for:

Experience: 8–12 years of hands-on RTL Synthesis

EDA exposure: Design compiler, PrimeTime, Tempus, Genus,

Multi-Node Design: Experience working with 16nm, 7nm… etc nodes.