ASIC Verification Intern: Build Next-Gen Networking Chips

Notre Dame; Roseville (CA); On-site; USD 48,000 - 56,000; Full time

Benefits offered by this job

Competitive hourly pay

Career development opportunities

Comprehensive benefits

Job summary

Hewlett Packard Enterprise (HPE) Aruba ASIC team is offering a summer internship in California for students pursuing a Bachelor’s or Master’s in Computer Engineering, CS, or EE. The role involves working on next-generation ASIC products and engaging in RTL/Physical Design, verification, and scripting across pre- and post-silicon stages.

You will perform schedule breakdowns, document generation, and collaborate with senior ASIC/VLSI engineers.

Qualifications

• Pursuing a Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical field.
• Completed at least the 3rd year of engineering courses.
• Basic programming or scripting knowledge such as Verilog, SystemVerilog, Python, PERL, TCL, C, or C++.
• Experience with hardware design.
• Strong interest in high-tech and learning.
• Excellent communication and interpersonal skills.
• Strong problem-solving and analytical abilities.
• Ability to work effectively within a team environment.

Responsibilities

• Work with the HPE Aruba ASIC development team on next-generation products.
• Contribute to a summer project in ASIC development activities.
• Engage in RTL/Physical Design, Pre-Silicon and Post-Silicon verification, Formal Verification, and script/tool development.
• Perform schedule breakdowns and document generation as needed.
• Collaborate and learn from senior members of the ASIC/VLSI team.

Skills

Verilog

SystemVerilog

Python

C

C++

Hardware design

Teamwork

Communication

TCL

PERL

Education

Pursuing Bachelor’s or Master’s in Computer Engineering/CS/EE

Job description

Hewlett Packard Enterprise (HPE) Aruba ASIC team is offering a summer internship in California for students pursuing a Bachelor’s or Master’s in Computer Engineering, CS, or EE. The role involves working on next-generation ASIC products and engaging in RTL/Physical Design, verification, and scripting across pre- and post-silicon stages.

You will perform schedule breakdowns, document generation, and collaborate with senior ASIC/VLSI engineers.