Post-Silicon ASIC Verification Intern (Hybrid)

HPE Aruba Networking; Roseville (CA); Hybrid; USD 48,000 - 56,000; Part time

Job summary

HPE Aruba Networking in Roseville, CA, seeks a ASIC Post-Si Verification Engineering Intern to join the ASIC/VLSI team for summer projects on next generation networking chips.

You will work with senior team members on RTL/Physical Design, Pre-Silicon and Post-Silicon verification, and may contribute to script/tool development, schedule breakdowns, and documentation. This internship emphasizes learning, collaboration, and real-world impact.

Qualifications

• Pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, or Electrical Engineering.
• At least 3rd Year of engineering courses completed.
• Strong interest in high-tech and a passion for learning.

Responsibilities

• RTL/Physical Design, Pre-Silicon verification tasks.
• Post-Silicon verification and Formal Verification work.
• Script & Tool development; schedule breakdowns and documentation.

Education

Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering

3rd Year of engineering courses completed

Tools

Verilog

SystemVerilog

Python

C/C++

Job description

HPE Aruba Networking in Roseville, CA, seeks a ASIC Post-Si Verification Engineering Intern to join the ASIC/VLSI team for summer projects on next generation networking chips.

You will work with senior team members on RTL/Physical Design, Pre-Silicon and Post-Silicon verification, and may contribute to script/tool development, schedule breakdowns, and documentation. This internship emphasizes learning, collaboration, and real-world impact.