ASIC Verification Intern — Hybrid (Roseville)

Hewlett Packard Enterprise; Roseville (CA); Hybrid; USD 48,000 - 56,000; Full time

Job summary

Hewlett Packard Enterprise's Aruba division in Roseville, CA is offering an ASIC Post-Si Verification Engineering Intern role designed as hybrid, with an expectation to work on average 2 days per week from an HPE office. The position targets students pursuing a Bachelor's or Master's degree in Computer Engineering, CS, or EE, with at least third year of study.

You will collaborate with the ASIC/VLSI team on RTL/Physical Design, Pre- and Post-Silicon verification, and tool scripting.

Qualifications

• Pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering or related field.
• At least 3rd Year of engineering courses completed.
• Basic programming or scripting knowledge (Verilog, SystemVerilog, Python, PERL, TCL, C, C++).

Responsibilities

• RTL/Physical Design
• Pre-Silicon verification
• Post-Silicon verification
• Formal Verification
• Script & Tool development
• Schedule breakdowns, document generation, and several other possible duties

Skills

Verilog

SystemVerilog

Python

PERL

TCL

C

C++

Education

Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering or related field

Job description

Hewlett Packard Enterprise's Aruba division in Roseville, CA is offering an ASIC Post-Si Verification Engineering Intern role designed as hybrid, with an expectation to work on average 2 days per week from an HPE office. The position targets students pursuing a Bachelor's or Master's degree in Computer Engineering, CS, or EE, with at least third year of study.

You will collaborate with the ASIC/VLSI team on RTL/Physical Design, Pre- and Post-Silicon verification, and tool scripting.