ASIC Verification Engineer

Links Technology Solutions, Inc.; Allentown (Lehigh County); On-site; USD 76,000 - 90,000; Full time

Benefits offered by this job

Health, life, vision, and dental insur

401K Matching

Job summary

Links Technology Solutions, Inc. in Allentown, PA is seeking an experienced ASIC Verification Engineer to help develop next-generation silicon for a major network manufacturer.

You will contribute to UVM-based verification environments and verification strategies that drive first-time-right results. The role requires 5–12 years in the industry, expertise in SystemVerilog and ASIC/SOC verification, and a collaborative approach with cross-functional teams to deliver robust test plans and

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Proficiency in System Verilog.
• Experience in identifying and resolving complex design and verification issues.
• Timing and gate level simulation experience; C coding for firmware delivery for post silicon bringup.
• Bachelor’s/Master’s degree in electrical or communications engineering or a related field.
• Experience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• System Verilog coding and debug.
• AI based CAD efficiency improvisation initiatives.
• High speed serial protocols (UCIe, PCIe).
• Analog debug experience including DAC/ADC and calibrations.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM

SystemVerilog

Python

Perl

C programming

Debugging

Cross-functional collaboration

Problem solving

Automation

AI CAD initiatives

High-speed protocols (PCIe/UCIe)

Analog debug (DAC/ADC)

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Tools

UVM Based testbench

SystemVerilog

Python

Perl

C

Job description

Title: ASIC VERIFICATION ENGINEER

Location: Allentown, PA

Pay Rate: $55-$65/HR

Duration: 1 yr extendable

Summary: Join our client's innovative team developing next-generation silicon solutions for a major network manufacturer. We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Description – ASIC Verification Engineer

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Qualifications – ASIC Verification Engineer

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block level to system level.
• Proficiency in System Verilog.
• Experience in identifying and resolving complex design and verification issues.
• Timing and gate level simulation experience.C coding for firmware delivery for post silicon bringup.
• Bachelors/master's degree in electrical or communications engineering or a related field.
• Experience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• System Verilog coding and debug.
• AI based CAD efficiency improvisation initiatives.
• High speed serial protocols preferred UCIe, PCIE.
• Analog debug experience including DAC/ADC & calibrations white-box verification.

Benefits:

• $55-$65/hr
• Available health, life, vision, and dental insurance
• 401K Matching