Senior SoC Physical Design & Timing Engineer

Apple Inc.; Waltham, Northern (MA, KY); Hybrid; USD 166,000 - 292,000; Full time

Job summary

Apple Inc. in Waltham, MA is seeking a SoC Physical Design Engineer specializing in STA/Timing to drive timing closures for complex SOC tapeouts. You will collaborate with design and physical teams to debug constraints, implement timing infrastructures, and create ECOs while developing robust scripts and methodologies.

Minimum BS with 10+ years of experience and strong TCL scripting are required. The role offers exposure to high-performance designs, noise modeling, and ECO techniques in a

Qualifications

• BS degree and 10+ years in ASIC/SoC design.
• Strong TCL scripting skills.
• Experience with large design STA and Timing Closure.
• Experience with timing of large high-performance SoC designs in sub-micron technologies.
• Deep understanding of noise, crosstalk, OCV and other timing modeling effects.
• Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation.
• Experience in ECO techniques and implementation.
• Experience with other scripting languages such as Perl or Python.

Responsibilities

• Understand constraints and debug timing with design teams.
• Collaborate with the Physical Design team to identify issues and best practices.
• Create timing ECOs for project tapeouts.
• Develop scripts and methodologies for analysis and runs.
• Create documentation and guidelines/specs.
• Analyze timing paths to identify key issues.
• Implement timing infrastructure.

Skills

TCL scripting

Strong communication

Education

BS in Electrical Engineering or related field

Tools

Perl

Python

Job description

Apple Inc. in Waltham, MA is seeking a SoC Physical Design Engineer specializing in STA/Timing to drive timing closures for complex SOC tapeouts. You will collaborate with design and physical teams to debug constraints, implement timing infrastructures, and create ECOs while developing robust scripts and methodologies.

Minimum BS with 10+ years of experience and strong TCL scripting are required. The role offers exposure to high-performance designs, noise modeling, and ECO techniques in a