ASIC Design Engineer – Fabric/Interconnect

Apple, Inc.; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple seeks a design engineer to drive RTL development, fabric integration and memory subsystem optimization for SoC blocks. You will own RTL generation, templating and scripting while coordinating with front-end, power and verification teams to ensure timing and quality.

The role requires collaboration with multi-disciplinary groups to deliver high-quality designs on schedule, with a strong emphasis on coherent/non-coherent interconnects and memory hierarchy.

Qualifications

• BS degree required with 0 years of experience.

Responsibilities

• Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC.
• Own RTL development design, templating, scripting and RTL generation.
• Collaborate with group to deliver results and hit schedules.

Skills

Cache Coherency

Memory Hierarchy

Large Designs

Synthesis & Verification

Interpersonal Skills

Self-starter

Front-end Tools

Education

BS Degree

Job description

At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy

Description

-Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).- Own all aspects of RTL development design, templating, scripting and RTL generation.- Work and collaborate with other designers in the group to deliver results.- Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block.- Work with front-end synthesis/STA teams to ensure timing for the block is met.- Work with power/performance and functional verification team to ensure high quality of the block.- Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process

Minimum Qualifications

• Minimum of BS + 0 years relevant industry experience.

Preferred Qualifications

• Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
• A consistent track record of delivering large, sophisticated designs in high volume production for low power applications
• Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time
• Strong interpersonal skills, as the candidate will work with diverse groups within the company
• Self-starter, highly motivated, highly organized, and schedule driven
• Familiarity with all front-end tools including lint, CDC, synthesis

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.