Senior Electrical Engineer - ASIC/FPGA (Onsite)

Collins Aerospace; Cedar Rapids (IA); On-site; USD 110,000 - 150,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Paid Vacation

401(k) Matching

Tuition Reimbursement

Life Insurance

Disability Coverage

Relocation Assistance

Job summary

Collins Aerospace in Cedar Rapids, IA, is seeking a senior digital design engineer to capture requirements and design, implement, verify, and integrate digital ASICs, FPGAs, and circuit boards, including RTL architecture, timing closure, and system integration. Candidates must hold a STEM degree with at least five years of relevant experience (or an advanced degree with at least three years), U.S.

citizenship, and an active Secret clearance after day one.

Qualifications

• Requires a STEM degree and at least five years of relevant experience, or an advanced degree and at least three years.
• U.S. citizenship and an active Secret clearance required after the first day.
• Experience with RTL coding and simulation in Verilog or VHDL, digital design and timing expertise.

Responsibilities

• Capture requirements and design, implement, verify, and integrate digital ASICs, FPGAs, and circuit boards, including RTL architecture, timing closure, and system integration.
• Improve design tools and practices, contribute to program estimates, and provide technical leadership by planning team work and reporting progress.

Skills

RTL Coding

Verilog

VHDL

SystemVerilog

ASIC Design

FPGA Design

Digital Circuit Architecture

Timing Analysis

Timing Closure

RTL Verification

Testbench Development

Simulation and Synthesis Tools

ASIC/FPGA Lab Validation

Design for Test

Git

Technical Leadership

Education

STEM degree

Advanced degree

Job description

Capture requirements and design, implement, verify, and integrate digital ASICs, FPGAs, and circuit boards, including RTL architecture, timing closure, and system integration. Improve design tools and practices, contribute to program estimates, and provide technical leadership by planning team work and reporting progress.

Requirements: Requires a STEM degree and at least five years of relevant experience, or an advanced degree and at least three years, along with U.S. citizenship and an active Secret clearance required after the first day. Candidates must have RTL coding and simulation experience in Verilog or VHDL, digital design and timing expertise, SystemVerilog testbench experience, familiarity with ASIC/FPGA tools, and revision control knowledge.

Key Skills: RTL Coding, Verilog, VHDL, SystemVerilog, ASIC Design, FPGA Design, Digital Circuit Architecture, Timing Analysis, Timing Closure, RTL Verification, Testbench Development, Simulation and Synthesis Tools, ASIC/FPGA Lab Validation, Design for Test, Git, Technical Leadership

Benefits: Medical Insurance, Dental Insurance, Vision Insurance, Paid Vacation, 401(k) Matching, Employer Retirement Contributions, Tuition Reimbursement, Student Loan Repayment, Life Insurance, Disability Coverage, Pet Insurance, Home and Auto Insurance, Accident Insurance, Critical Illness Insurance, Group Legal Insurance, Identity Theft Protection, Parental Leave, Adoption Assistance, Employee Assistance Plan, Wellness Rewards, Virtual Doctor Visits, Child and Elder Care Services, Second Opinion Medical Services, Relocation Assistance