Senior Design Verification Engineer

The Judge Group; United States; Remote; USD 83,000 - 124,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Job summary

The Judge Group seeks an experienced Senior Verification Engineer to join an ASIC/SoC verification team. You will help define verification methodologies, build infrastructure, and drive complex digital verification across IP, blocks, and the full SoC.

Remote work is offered with potential for on-site relocation if converted to full-time. Ideal candidates bring strong SystemVerilog/UVM expertise, formal verification knowledge, and experience with metric-driven verification.

Qualifications

• Bachelor's degree or equivalent in a technical field.
• 5+ years in ASIC or SoC functional verification.
• Strong SystemVerilog/UVM background.
• Experience with verification environments and testbenches.
• Knowledge of functional coverage and metric-driven verification.

Responsibilities

• Own verification planning, execution, and sign-off for IPs and subsystems.
• Develop test plans, coverage strategies, and verification methodologies.
• Translate design specs into measurable verification objectives.
• Create and maintain verification environments, scoreboards, and monitors.
• Perform constrained-random, formal, and directed verification.
• Drive coverage closure and regression readiness.

Skills

Verific ation planning

Mentoring

Cross-functional collaboration

Debug RTL

Signal analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog

UVM

Assertions (SVA)

Formal Verification

Constrained-Random Verification

Job description

Location: Remote (Candidates must be open to relocating for an on-site role if converted to a full-time employee)

Schedule: Monday-Friday, Standard Business Hours

Duration: 6+ Month Contract with potential for extension or permanent conversion based on performance

About the Role

We are seeking an experienced Senior Verification Engineer to join a cutting-edge ASIC/SoC development team working on next-generation high-performance silicon products. This role offers the opportunity to help define verification methodologies, infrastructure, and best practices from the ground up while contributing to complex digital systems spanning IP, subsystem, and full SoC verification.

The ideal candidate will have strong expertise in ASIC/SoC functional verification, SystemVerilog/UVM, formal verification methodologies, and metric-driven verification strategies. Experience with wireless, modem, DSP, or networking technologies is a plus but not required.

What You'll Do

• Own verification planning, execution, and sign-off for complex IPs, blocks, and subsystems.
• Develop comprehensive test plans, coverage strategies, and verification methodologies.
• Translate design specifications into measurable verification objectives and coverage goals.
• Create and maintain verification environments, scoreboards, protocol monitors, assertions, and reference models.
• Perform constrained-random, formal, and directed verification to ensure design quality.
• Drive functional coverage closure and regression readiness.
• Debug RTL and system-level issues while collaborating closely with design and architecture teams.
• Build reusable verification infrastructure across IP, subsystem, and SoC levels.
• Support CI/CD and automated regression environments.
• Leverage AI-assisted tools for stimulus generation, regression analysis, and coverage optimization.
• Mentor junior engineers and contribute to verification best practices and methodology improvements.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 5+ years of experience in ASIC or SoC functional verification.
• Strong hands-on experience with SystemVerilog and UVM verification methodologies.
• Experience developing and maintaining advanced verification environments and testbenches.
• Strong understanding of assertions, functional coverage, and metric-driven verification.
• Experience verifying complex digital datapath and control logic.
• Proficiency in RTL and system-level debugging.

Preferred Qualifications

• Experience with wireless communications, networking, modem, baseband, DSP, or related technologies.
• Background in formal verification techniques and production silicon verification.
• Experience verifying high-performance interconnects, NoCs, or complex SoC architectures.
• Knowledge of CDC verification, security verification, and protocol compliance testing.
• Experience with fault-tolerant designs, ECC, redundancy mechanisms, or fault injection techniques.
• Familiarity with firmware-driven verification and processor-based SoC validation.
• Experience using AI/ML/LLM-based tools for verification automation, regression triage, or coverage analysis.

Preferred Skills & Tools

Languages & Methodologies: SystemVerilog, UVM, Assertions (SVA), Formal Verification, Constrained-Random Verification

Why Apply?

• Opportunity to influence verification architecture and methodology from the beginning.
• Work on advanced ASIC and SoC technologies.
• Exposure to AI-driven verification workflows and automation.
• Collaborative environment with highly experienced engineering teams.
• Long-term contract potential with possibility of permanent employment.

Benefits Featured

Medical, Dental , and Vision Insurance is offered to qualified candidates.