ASIC Power Design Engineer - Low-Power Innovator

Cisco Systems, Inc; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Cisco Systems, Inc. is seeking a power-optimized ASIC design engineer to contribute to low-power methodologies and RTL-to-physical collaboration on advanced silicon. You will perform multi‑domain power analysis and help drive power-aware optimization across chip blocks and full chips.

The role emphasizes automation using Python, TCL, and Perl, with strong emphasis on Linux environments and modern EDA tools, in a fast-paced hardware team delivering next‑gen Cisco silicon.

Qualifications

• Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience.
• Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs).
• Proficiency with hardware description languages (SystemVerilog / Verilog).
• Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
• Familiarity with Linux/Unix development environment

Responsibilities

• Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent).
• Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower across operating modes and corners.
• Collaborate with RTL design and architecture teams to identify power bottlenecks and guide RTL/micro-architectural optimizations.
• Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA).
• Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
• Participate in post-silicon power and performance validation and correlation against pre-silicon PrimePower models

Skills

Low-power design

SystemVerilog

Python

TCL

Linux

Education

Bachelor's degree in ASIC/Power Design

Master's degree in related field

Tools

Design Compiler

Fusion Compiler

PrimeTime

StarRC

IC Validator

Cadence Innovus

Job description

Cisco Systems, Inc. is seeking a power-optimized ASIC design engineer to contribute to low-power methodologies and RTL-to-physical collaboration on advanced silicon. You will perform multi‑domain power analysis and help drive power-aware optimization across chip blocks and full chips.

The role emphasizes automation using Python, TCL, and Perl, with strong emphasis on Linux environments and modern EDA tools, in a fast-paced hardware team delivering next‑gen Cisco silicon.