ASIC Power Analysis Engineer (Physical Design & Low Power)

Intelliswift - An LTTS Company; United States; Hybrid; USD 160,000 - 200,000; Full time

Job summary

Intelliswift - An LTTS Company is seeking an experienced ASIC Power Analysis Engineer in Redmond, WA, on a hybrid basis. The role focuses on power estimation, low-power methodologies, and flow-level optimization across RTL and physical design teams to deliver high-performance, power-efficient silicon.

The candidate should have 10+ years of ASIC power/physical design experience, strong scripting (Python, TCL), and familiarity with UPF and Synopsys power tools.

Qualifications

• 10+ years of ASIC power/physical design experience.
• Experience with power estimation, synthesis, and flows.
• Strong scripting and data analysis skills (Python, TCL).
• Knowledge of UPF, power optimization, and backend tradeoffs.

Responsibilities

• Develop, maintain, and enhance ASIC power analysis flows across RTL and gate levels.
• Generate switching activity data from simulations for power estimation.
• Correlate RTL power estimates with gate-level results and identify root causes.
• Analyze clock, datapath, memory, and leakage power to spot optimization opportunities.
• Drive power reduction initiatives such as clock gating and datapath gating.
• Automate analysis, reporting, and data processing with Python, TCL, and Linux scripts.

Skills

ASIC Power Analysis

Physical Design

TCL Scripting

Python Scripting

Low Power Design

Power Optimization

Synthesis

UPF

Tools

PrimePower

PTPX

PPRTL

Synopsys Power Analysis Tools

Job description

Job Title: ASIC Power Analysis Engineer (Physical Design & Low Power)

Location: Redmond - WA (Hybrid)

Duration: 12 Months+

We are seeking an experienced ASIC Power Analysis Engineer to support the development of next-generation silicon solutions for advanced consumer and computing platforms. This role focuses on power analysis, optimization, and methodology development across the ASIC design flow, working closely with architecture, RTL, verification, and physical design teams to deliver high-performance, power-efficient designs.

The ideal candidate will have deep expertise in ASIC power estimation, low-power methodologies, physical design concepts, and scripting automation.

Top 3 Skills:

• ASIC Power Analysis
• Physical Design
• TCL/Python Scripting

Preferred Skills

• Low Power Design
• Power Optimization
• Synthesis
• UPF

Must-Have Requirements

• 10+ years of ASIC Power Engineering, CAD Engineering, or Physical Design experience
• Experience with power estimation, synthesis, and physical design flows
• Strong scripting and data analysis skills (Python, TCL)
• Knowledge of power optimization methodologies, UPF, and backend implementation tradeoffsExperience with Synopsys power analysis tools (PrimePower/PTPX, PPRTL preferred)

Responsibilities

• Develop, maintain, and enhance ASIC power analysis flows at both RTL and gate-level.
• Generate and manage switching activity data from simulation environments for power estimation and analysis.
• Correlate RTL power estimates with signoff-quality gate-level power results and identify root causes of discrepancies.
• Perform detailed power breakdowns across blocks, hierarchies, and workloads to identify key power contributors.
• Analyze clock, datapath, memory, and leakage power, and recommend optimization opportunities.
• Drive power reduction initiatives including clock gating, datapath gating, and low-power implementation strategies.
• Automate analysis, reporting, and data processing workflows using Python, TCL, and Linux-based scripting environments.
• Support synthesis, timing, physical design, and power optimization activities.
• Perform report processing, data extraction, visualization, and trend analysis.
• Assist with RTL, netlist, and power-intent implementation activities.
• Document methodologies, findings, and recommendations, and communicate results to cross-functional engineering teams.