Low-Power ASIC RTL Design Engineer

Lancesoft; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Lancesoft is seeking a digital design engineer in Santa Clara, CA, to drive low-power design strategies for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area, ensuring reliable silicon meeting product requirements.

You will work with RTL, physical design, and verification teams across time zones, focusing on power reduction, timing closure, and robust test planning. Strong scripting and experience with advanced process nodes are a plus.

Qualifications

• Strong background in ASIC synthesis and STA (Timing Closure).
• Experience with low-power design techniques (clock gating, multi-Vt, power gating, multi-voltage).
• Familiarity with UPF/CPF power intent specification and verification.

Responsibilities

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and STA to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Collaborate with RTL, physical design, and verification teams to meet timing and power requirements.
• Run UPF/CPF power intent checks and validate correct power implementation.
• Support sign-off activities for lint, CDC, synthesis, timing, and power closure.
• Automate power and timing workflows to improve efficiency.
• Build test plan documentation considering interactions with other features.

Skills

ASIC design

Power optimization

Timing closure

RTL design

Tools

Synopsys Design Compiler

PrimeTime

PrimePower

Power Artists

UPF/CPF tools

Python

TCL

Job description

Lancesoft is seeking a digital design engineer in Santa Clara, CA, to drive low-power design strategies for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area, ensuring reliable silicon meeting product requirements.

You will work with RTL, physical design, and verification teams across time zones, focusing on power reduction, timing closure, and robust test planning. Strong scripting and experience with advanced process nodes are a plus.