ASIC Power Design Engineer II - LowPower & PVT Optimizations

Cisco Systems, Inc.; San Jose (CA); On-site; USD 110,000 - 170,000; Full time

Job summary

Cisco Systems, Inc. is seeking a power-design engineer to implement low‑power techniques, perform comprehensive power analyses, and collaborate with RTL/architecture to optimize performance and energy use. You will also develop automated workflows using Python, TCL, and Perl to streamline EDA tasks.

The role targets recent graduates or current students with a strong background in ASIC/Power design, Linux environments, and scripting.

Qualifications

• Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience.
• Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells).
• Proficiency with hardware description languages (SystemVerilog / Verilog).
• Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
• Familiarity with Linux/Unix development environment

Responsibilities

• Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, DVS, UPF/CPF).
• Perform block- and full-chip power analysis and estimation across modes and corners.
• Collaborate with RTL design/architecture to identify power bottlenecks and optimizations.
• Achieve timing closure, signal integrity, and power targets across FinFET/GAA nodes.
• Develop and maintain automated design/analysis workflows using Python, TCL, and Perl.
• Participate in post-silicon power/performance validation against pre-silicon models

Skills

SystemVerilog/Verilog

Low-power design

Linux/Unix

Scripting (TCL/Python/Perl)

Education

Bachelor’s + 2 years experience or Master’s degree

Tools

Synopsys PrimePower

Synopsys Design Compiler

Cadence tools (Innovus)

Job description

Cisco Systems, Inc. is seeking a power-design engineer to implement low‑power techniques, perform comprehensive power analyses, and collaborate with RTL/architecture to optimize performance and energy use. You will also develop automated workflows using Python, TCL, and Perl to streamline EDA tasks.

The role targets recent graduates or current students with a strong background in ASIC/Power design, Linux environments, and scripting.