Senior ASIC/RTL Design Engineer – Low-Power & PPA

TekWissen LLC; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

TekWissen Group leads global staffing and supports a major American semiconductor client in Santa Clara, CA. The role focuses on driving low-power strategies, synthesis, and timing closure for complex SoC/IP designs.

Collaboration with RTL, physical, and verification teams ensures robust PPA and reliable silicon for advanced nodes. The ideal candidate excels in digital design, power optimization, and timing closure, and is adept with Verilog/SystemVerilog, scripting, and modern EDA tools.

Qualifications

• Strong background in ASIC design and STA.
• Experience with UPF/CPF power intent verification.
• Proficiency in Verilog/SystemVerilog.
• Experience with advanced process nodes is a plus.
• Scripting for flow automation (TCL/Python/Perl).

Responsibilities

• Develop and implement power reduction strategies for SoC/IP.
• Perform synthesis and STA to meet PPA targets.
• Analyze dynamic and leakage power using industry tools.
• Collaborate with RTL, physical design, and verification teams.
• Run UPF/CPF power checks and validate power intent.
• Support sign-off for lint, CDC, synthesis, timing, and power.
• Automate power and timing workflows to improve efficiency.
• Build test plans and document hardware interactions.

Skills

Digital design

Power optimization

Timing closure

RTL coding

Verilog/SystemVerilog

Scripting languages

C/C++

Education

B.S. in Electrical Engineering or Computer Science

Tools

Synopsys Design Compiler

PrimeTime

PrimePower

Power Artists

Job description

TekWissen Group leads global staffing and supports a major American semiconductor client in Santa Clara, CA. The role focuses on driving low-power strategies, synthesis, and timing closure for complex SoC/IP designs.

Collaboration with RTL, physical, and verification teams ensures robust PPA and reliable silicon for advanced nodes. The ideal candidate excels in digital design, power optimization, and timing closure, and is adept with Verilog/SystemVerilog, scripting, and modern EDA tools.