ASIC/RTL Design Engineer 5

Managed Staffing; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Managed Staffing, Inc. in San Jose, CA seeks a skilled ASIC power/SoC design engineer to drive low-power strategies, synthesis, and timing closure for complex designs.

You will collaborate with RTL, physical design, and verification teams to optimize PPA, implement UPF/CPF power intents, and automate power and timing workflows in a fast-paced semiconductor environment.

Qualifications

• Strong background in ASIC synthesis and STA.
• Hands-on expertise with EDA tools such as Design Compiler, PrimeTime, PrimePower, Power Artist, or equivalent.
• Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
• Familiarity with UPF/CPF power intent specification and verification.
• Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
• Proficiency in scripting languages (TCL, Perl, Python, or Shell).
• Exposure to floorplanning, place-and-route, and ECO flows is desirable.
• Knowledge of low-power design methodologies and trade-offs.
• Prior leadership or cross-functional collaboration experience is a plus.

Responsibilities

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and static timing analysis to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Coordinate with RTL, physical design, and verification teams to meet timing and power requirements.
• Run UPF/CPF power intent verification and validate power semantics.
• Support sign-off activities for lint, CDC, synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test plan documentation accounting for interactions with other features.

Skills

ASIC power optimization

STA (static timing analysis)

Verilog/SystemVerilog

Digital design fundamentals

RTL coding

Scripting (TCL, Python, Perl)

Flow automation

Leadership / mentorship (asset)

Power optimization techniques

Clock gating / multi-Vt / multi-volt

Tools

Synopsys Design Compiler

PrimeTime

PrimePower

PowerArtist

Job description

THE ROLE:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

THE PERSON:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

KEY RESPONSIBILITIES:

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
• Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
• Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test plan documentation, accounting for interactions with other features, the hardware.

PREFERRED EXPERIENCE:

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
• Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
• Familiarity with UPF/CPF power intent specification and verification.
• Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
• Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
• Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
• Exposure to floorplanning, place-and-route, and ECO flows is desirable.
• Knowledge of low-power design methodologies and trade-offs.
• Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
• Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment.