ASIC Physical Design Engineer – Maynard, MA or Austin, TX

WarmStart Ltd; Northern (KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Cisco Systems is seeking an ASIC Physical Design Engineer to join the team in Maynard, MA or Austin, TX. You will own RTL-to-GDSII implementations for cutting-edge nodes and collaborate with RTL/DFT teams to ensure robust timing and area goals.

Responsibilities include floor planning, P&R, STA, ECOs, and script-driven automation to improve flows. Requires a strong ASIC design background and tool expertise in Cadence/Synopsys/Mentor ecosystems.

Qualifications

• Bachelor's degree in Computer or Electrical Engineering with 5+ years of ASIC design experience.
• Master's degree with 3+ years of experience also acceptable.
• Hands-on experience in ASIC physical design and implementation.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies.
• Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Skills

RTL-to-GDSII

Floor planning

STA timing

TCL scripting

DC/FC synthesis

Formal verification

Power integrity

Physical verification

Education

Bachelor's in EE/CE

Master's in EE/CE

Tools

Cadence Innovus

Synopsys ICC2

Mentor Calibre

PrimeTime

Tempus

Voltus

Redhawk

Job description

ASIC Physical Design Engineer – Maynard, MA or Austin, TX

Cisco Systems, 12515 Research Blvd Bldg 4, Austin, TX 78759

Job Description:

Join the Cisco Acacia Communications team as a Physical Design Engineer, where you will contribute to the development of intelligent transceivers for high-speed fiber optic transmission. This role offers a unique blend of resources from a large organization and the dynamic culture of a smaller team, focusing on advanced semiconductor nodes.

Responsibilities:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies.
• Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Qualifications:

• Bachelor's degree in Computer or Electrical Engineering with 5+ years of experience, or a Master's degree with 3+ years of experience.
• Hands-on experience in ASIC physical design and implementation.

Skills:

• Experience with place & route using tools such as Cadence Innovus, Synopsys ICC2, or equivalent.
• Familiarity with industry standard CAD methodologies (Cadence, Synopsys, or Mentor).
• Experience with floor planning & partitioning, formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR.
• Proficiency in Static Timing Analysis tools such as PrimeTime-DMSA or Tempus.
• Scripting experience in languages such as TCL, Perl, or Python.
• Synthesis experience with Synopsys DC/FC.
• Formal Verification experience using tools like Synopsys Formality or Cadence LEC.
• Experience with Power Integrity tools such as Apache Redhawk or Voltus.
• Physical Verification DRC/LVS experience with tools like Synopsys ICV or Mentor Calibre.