Senior ASIC Physical Design Technical Lead

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 200,000 - 260,000; Full time

Job summary

Cisco's Common Hardware Group in San Jose, CA is seeking a Senior ASIC Physical Design Technical Lead to drive fullchip floorplanning and RTL-to-GDSII implementation for networking ASICs.

The role requires extensive physical design experience, collaboration with RTL, DFT, EDA vendors, and applying low-power methodologies to optimize performance, power, and die size in advanced node processes.

Qualifications

• 12+ years of physical design experience or equivalent with advanced process nodes.
• Proven expertise in RTL-to-GDSII/flow for 7nm+ processes.
• Hands-on with major EDA tools (Innovus, Tempus/PrimeTime, Calibre, Pegasus).

Responsibilities

• Understand architecture and IP placement for fullchip floorplan.
• Collaborate with system and package design teams on floorplan requirements.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning.
• Execute RTL-to-GDSII flow focusing on performance, power, die size.
• Analyze tool flows and methodologies for efficiency improvements.
• Coordinate with RTL, DFT, EDA vendors to enable best-in-class methodology.
• Apply low-power design methodologies with foundry/IP signoff processes.

Skills

Hierarchical design

Timing closure

Power integrity

Static timing analysis

Timing constraints

Fullchip floorplanning

Power grid planning

Custom clock design

Python

AI tools

Education

Bachelor’s degree in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Senior ASIC Physical Design Technical Lead

Join Cisco's Common Hardware Group (CHG) as a key contributor in designing and developing advanced ASICs for networking hardware. This role focuses on fullchip floorplanning, RTL-to-GDSII implementation, and collaboration with various teams to enhance design methodologies. Ideal candidates will have extensive experience in physical design and a passion for innovation in the AI era.

Responsibilities:

• Understand architecture and IP placement constraints for fullchip floorplan.
• Collaborate with system and package design teams to incorporate requirements into the floorplan.
• Perform hierarchical implementation flow including partitioning, pin assignment, and clock planning.
• Execute RTL-to-GDSII implementation focusing on performance, power, and die size optimization.
• Analyze tool flows and methodologies to identify and implement efficiency improvements.
• Work closely with RTL, DFT, implementation, and EDA vendors to enable best-in-class design methodology.
• Utilize low-power design methodologies and collaborate with foundry and IP vendors for signoff methodologies.

Qualifications:

• Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, or Master’s Degree with 8+ years, or PhD with 5+ years.
• Experience with Fullchip activities and RTL-to-GDSII flow in advanced process technologies (7nm/5nm/3nm).
• Proficiency with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus.

Skills:

• Experience in hierarchical design, timing closure, and power integrity analysis.
• Knowledge of static timing analysis and defining timing constraints.
• Expertise in fullchip floor-planning and power grid planning.
• Familiarity with custom clock designs at the chip level.
• Proficiency in Python and AI tools for productivity improvements.

Find the Right Semiconductor Partner

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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