Senior ASIC Physical Design Engineer - RTL-to-GDSII

Cisco; Austin (TX); On-site; USD 150,000 - 240,000; Full time

Job summary

Cisco is seeking a Physical Design Engineer in Austin to lead RTL-to-GDSII work for sub-16nm to 2nm nodes. You will drive floorplanning, place-and-route, clock/power distribution, and timing convergence across teams to deliver high-performance networking chips.

The role requires hands-on ASIC design experience, emphasis on floorplanning and STA, and collaboration with RTL, DFT, and EDA partners. Cisco provides a comprehensive benefits package and a path for technical growth.

Qualifications

• Minimum: Bachelors in Electrical Engineering with 5+ years of related experience OR Masters with 2+ years OR PhD with 0+ years.
• Hands-on experience in ASIC physical design and implementation.
• Experience with hierarchical floorplanning, clock/power distribution, global signal and I/O planning, physical convergence, timing closure.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place-and-route, clock and power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps; recommend tool/flow/methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design efficiency.

Skills

ASIC physical design

Floorplanning

Timing closure

Power integrity

High-gate designs

Education

Bachelors in Electrical Engineering

Masters in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys FC

PrimeTime

Mentor Calibre

Genus

Job description

Cisco is seeking a Physical Design Engineer in Austin to lead RTL-to-GDSII work for sub-16nm to 2nm nodes. You will drive floorplanning, place-and-route, clock/power distribution, and timing convergence across teams to deliver high-performance networking chips.

The role requires hands-on ASIC design experience, emphasis on floorplanning and STA, and collaboration with RTL, DFT, and EDA partners. Cisco provides a comprehensive benefits package and a path for technical growth.