Physical Design Engineer / Lead

Highbrow Technology Inc; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Highbrow Technology Inc. in San Jose, CA is seeking an experienced Physical Design Engineer / Lead to drive ASIC physical design from floorplanning through timing closure and signoff.

You will collaborate with RTL, STA, and verification teams, optimize power integrity, and implement designs using Cadence Innovus among other tools. Strong problem-solving and communication skills are essential. This role also offers leadership in cross-functional design flow improvements.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• Hands-on experience in Physical Design from RTL-to-GDSII.
• Experience with floorplanning, placement, CTS, routing, and timing closure.
• Strong problem-solving and debugging skills.
• Excellent communication and teamwork abilities.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Power planning

Physical signoff

RTL-to-GDSII

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Cadence Innovus

Job description

We are looking for experienced Physical Design Engineer / Lead. The ideal candidate will have hands-on experience in ASIC physical design and implementation, from floorplanning through timing closure and physical signoff.

Requirements:

• Experience in Physical Design and RTL-to-GDSII implementation.
• Hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
• Experience with industry-standard physical design tools such as Cadence Innovus.
• Strong understanding of power planning, power grid design, and physical implementation methodologies.
• Experience with Static Timing Analysis (STA) and timing optimization.
• Hands-on experience with DRC/LVS, LEC, and physical design signoff.
• Experience with clock tree synthesis (CTS) and clock optimization.
• Knowledge of IR drop, electromigration (EM), and power integrity is a plus.
• Experience with hierarchical physical design is a plus.
• Experience with multiple technology nodes and tape-outs is a plus.
• Familiarity with low-power design techniques such as power gating, multi-Vt, and voltage islands is a plus.
• Scripting/programming experience using Tcl, Perl, Python, or similar languages is a plus.
• Experience in physical design flow development, automation, or methodology improvement is a plus.
• Ability to work closely with RTL, STA, DFT, verification, and other cross-functional teams.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Relevant experience in Physical Design.
• Strong problem-solving and debugging skills.
• Good understanding of the physical design flow from netlist to GDSII.
• Excellent communication and teamwork skills.