Senior ASIC Physical Design Engineer – High-Speed Transceivers

WarmStart Ltd; Northern (KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Cisco Systems is seeking an ASIC Physical Design Engineer to join the team in Maynard, MA or Austin, TX. You will own RTL-to-GDSII implementations for cutting-edge nodes and collaborate with RTL/DFT teams to ensure robust timing and area goals.

Responsibilities include floor planning, P&R, STA, ECOs, and script-driven automation to improve flows. Requires a strong ASIC design background and tool expertise in Cadence/Synopsys/Mentor ecosystems.

Qualifications

• Bachelor's degree in Computer or Electrical Engineering with 5+ years of ASIC design experience.
• Master's degree with 3+ years of experience also acceptable.
• Hands-on experience in ASIC physical design and implementation.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies.
• Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Skills

RTL-to-GDSII

Floor planning

STA timing

TCL scripting

DC/FC synthesis

Formal verification

Power integrity

Physical verification

Education

Bachelor's in EE/CE

Master's in EE/CE

Tools

Cadence Innovus

Synopsys ICC2

Mentor Calibre

PrimeTime

Tempus

Voltus

Redhawk

Job description

Cisco Systems is seeking an ASIC Physical Design Engineer to join the team in Maynard, MA or Austin, TX. You will own RTL-to-GDSII implementations for cutting-edge nodes and collaborate with RTL/DFT teams to ensure robust timing and area goals.

Responsibilities include floor planning, P&R, STA, ECOs, and script-driven automation to improve flows. Requires a strong ASIC design background and tool expertise in Cadence/Synopsys/Mentor ecosystems.