ASIC Physical Design Engineer I (Internship)

Cisco Systems, Inc.; Maynard (MA); On-site; USD 44,000 - 185,000; Part time

Job summary

Cisco Systems, Inc. is seeking an undergraduate intern to join the Acacia PD team and gain hands-on experience in ASIC physical design from RTL to GDSII.

You will work on front-end architecture reviews, physical implementation, and signoff activities under the guidance of senior engineers. This internship emphasizes learning in a fast-paced environment, with exposure to floorplanning, placement, routing, timing closure, and verification.

Qualifications

• Must be an undergraduate student in a CS/EE-related program
• Experience with RTL to GDSII is preferred
• Familiarity with SSTA, timing closure, and design constraints is a plus

Responsibilities

• Work with Front-End teams to understand design architecture and ensure optimal physical implementation
• Gate level netlist synthesis (physical synthesis)
• Physical implementation (floorplanning, placement, CTS, routing)
• Power, performance and area optimization of design
• Static Timing analysis and signoff closure
• Physical verification and signoff closure
• EMIR analysis and signoff closure

Skills

RTL to GDSII knowledge

Static Timing Analysis

P&R flow experience

Problem solving

Team collaboration

Education

Undergraduate degree in Computer Science / Electrical Engineering

Currently enrolled in Associate or Bachelor's program

Tools

Perl

Tcl

Python

Shell

Job description

Cisco Systems, Inc. is seeking an undergraduate intern to join the Acacia PD team and gain hands-on experience in ASIC physical design from RTL to GDSII.

You will work on front-end architecture reviews, physical implementation, and signoff activities under the guidance of senior engineers. This internship emphasizes learning in a fast-paced environment, with exposure to floorplanning, placement, routing, timing closure, and verification.