ASIC Physical Design Engineer - High-Performance SoCs

QUALCOMM, Inc.; San Diego (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, California, is seeking highly skilled Physical Design Engineers across multiple career levels to join its ASIC implementation team.

You will contribute to physical design, floorplanning, place & route, timing closure, and signoff for high-performance SoCs and IP blocks, collaborating with architecture, RTL, CAD, verification, and product teams, using Cadence Innovus and Synopsys Fusion Compiler to achieve power-efficient designs.

Responsibilities

• Contribute to physical design, floorplanning, and place & route.
• Achieve timing closure and signoff for high-performance SoCs and IP blocks.
• Collaborate with architecture, RTL, CAD, verification, and product teams.

Tools

Cadence Innovus

Synopsys Fusion Compiler

Job description

Qualcomm Technologies, Inc. in San Diego, California, is seeking highly skilled Physical Design Engineers across multiple career levels to join its ASIC implementation team.

You will contribute to physical design, floorplanning, place & route, timing closure, and signoff for high-performance SoCs and IP blocks, collaborating with architecture, RTL, CAD, verification, and product teams, using Cadence Innovus and Synopsys Fusion Compiler to achieve power-efficient designs.