Synthesis & Physical Design Engineer – High-Speed Silicon

NVIDIA Gruppe; Westford (MA); On-site; USD 116,000 - 189,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Physical Design Engineer with synthesis expertise to join our Networking Silicon team in the United States. You will own RTL-to-gate synthesis, QoR convergence, and drive flows across RTL, timing, and physical design to meet performance and power targets.

Collaboration with RTL, timing, architecture, and physical teams is essential for successful silicon tapeouts and robust margins. We offer a world‑class team, competitive compensation, equity, and a comprehensive benefits

Qualifications

• BSEE, MSEE, or equivalent experience.
• 2+ years of synthesis and physical implementation on advanced process nodes.
• Proficiency with Synopsys Fusion Compiler or Cadence Genus.
• Experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.
• Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.
• Proficiency in Python, Perl, Tcl, and Make.
• Excellent communication and cross-functional collaboration skills.

Responsibilities

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks.
• Optimize synthesis strategies to meet performance, power, and area targets.
• Analyze design bottlenecks and QoR regressions with RTL, timing, architecture, and physical design teams.
• Support physical implementation from floorplanning to timing closure.
• Automate design setup, execution, reporting, and issue triage while improving methodologies.

Skills

Timing analysis

Debugging

Communication

Collaboration

Education

BSEE / MSEE or equivalent

Tools

Synopsys Fusion Compiler

Cadence Genus

Python

Perl

Tcl

Make

Job description

NVIDIA is seeking a Physical Design Engineer with synthesis expertise to join our Networking Silicon team in the United States. You will own RTL-to-gate synthesis, QoR convergence, and drive flows across RTL, timing, and physical design to meet performance and power targets.

Collaboration with RTL, timing, architecture, and physical teams is essential for successful silicon tapeouts and robust margins. We offer a world‑class team, competitive compensation, equity, and a comprehensive benefits