ASIC Engineer, Power

Meta; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Equity

Bonus

Benefits

Job summary

Meta is seeking an ASIC Engineer specialized in power on the EDA Infrastructure team in Austin to build and optimize power analysis flows and signoff methodologies across RTL to GDSII. You will collaborate with RTL, physical design, and verification teams to reduce power hotspots and drive efficiency in custom ASIC designs.

The role involves developing scripts, evaluating EDA tools, and defining power methodology guidelines to support next-generation silicon design and verification at Meta.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.
• 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff.
• Experience developing or maintaining EDA flows for power analysis using tools such as PrimePower or Voltus.
• Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows.
• Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows.
• Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs.
• Degree must be completed prior to joining Meta.

Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools.
• Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow.
• Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs.
• Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround timeli>
• Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations.
• Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages.
• Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders.
• Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities.
• Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques.
• Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Skills

Power analysis

EDA tooling

Python scripting

Tcl scripting

Shell scripting

Power integrity

Education

Bachelor's degree in CS/CE or related field

Tools

Synopsys PrimePower

Cadence Voltus

UPF/CPF

Job description

Meta is building custom silicon to power the infrastructure that underlies its family of products and services. As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and maintain power analysis and optimization flows that enable silicon engineers across the organization to accurately model, estimate, and reduce power consumption in custom ASIC designs. In this role, you will work at the intersection of EDA tooling, physical design, and power methodology, helping to define the infrastructure that shapes how Meta's next-generation chips are designed and verified.

ASIC Engineer, Power Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools
• Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow
• Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs
• Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround timeli>
• Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations
• Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages
• Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders
• Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities
• Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques
• Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff
• Experience developing or maintaining EDA flows for power analysis using tools such as Synopsys PrimePower, Cadence Voltus, or equivalent
• Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows
• Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows
• Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs
• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta

Preferred Qualifications

• Experience evaluating and qualifying new EDA tools or methodologies in a production silicon environment
• Familiarity with custom or semi-custom design flows for high-performance computing or data center silicon
• Experience with low-power design techniques including clock gating, power gating, multi-voltage domain design, and dynamic voltage and frequency scaling
• Background in developing internal EDA infrastructure tooling or flow automation at scale across multiple concurrent design projects

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$114,000/year to $172,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.