ASIC Engineer, Architecture

Meta; Austin (TX); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions that power AI and data center workloads. We are seeking an ASIC Engineer specializing in architecture, performance, and modeling to define performance modeling methodologies and long-term silicon roadmap strategy.

You will develop cycle-accurate models, collaborate across architecture, RTL, and physical design, and mentor others in modeling best practices while driving improvements from design to silicon.

Qualifications

• Bachelor's degree in CS/CE or related field or equivalent practical experience.
• 6+ years in ASIC design or silicon engineering.
• Proficiency in C++ and Python for sim/models/automation.
• 5+ years in ASIC performance modeling or pre-silicon simulation.
• Experience with data-center/AI workloads on custom silicon.
• Experience with cycle-accurate or transaction-level models (C++/SystemC).
• Experience defining microarchitectural specs across teams.
• Experience with assembly languages and compiler tech.

Responsibilities

• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O domains.
• Define and own the performance modeling strategy for custom infrastructure ASICs and develop cycle-accurate and transaction-level environments.
• Develop and maintain C++ models of AI chip IPs and subsystems for exploration and software development.
• Develop workloads and kernels for ML training and inference.
• Establish performance analysis methodologies, benchmarking and bottleneck techniques across the ASIC pipeline.
• Collaborate with architecture, RTL, and physical design to translate performance requirements into specs.
• Partner with software and systems teams to co-optimize workload scheduling, firmware and driver behavior.
• Lead cross-functional reviews and communicate results to engineering leadership.
• Define long-term performance modeling infrastructure roadmaps and tooling investments.
• Mentor engineers on performance modeling techniques and calibration.

Skills

C++

Python

SystemC

Performance modeling

Microarchitecture

Education

Bachelor's degree in Computer Science or related field

Tools

SystemVerilog

Simulation Environments

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

ASIC Engineer, Architecture Responsibilities

• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions
• Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments
• Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development
• Develop low-level workloads and kernels for machine learning training and inference applications
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics
• Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership
• Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments
• Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices
• Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in ASIC design, silicon engineering, or a related technical field
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnects
• Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams
• Experience with assembly programming languages, and compiler technologies

Preferred Qualifications

• Experience with AI numerics, data types, math functions, and precision/accuracy analysis
• Experience writing and optimizing compute/collective kernels in CUDA or equivalent GPU programming frameworks
• Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
• Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis
• Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies
• Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows
• Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$146,000/year to $209,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.