ASIC Design Verification Engineer

Meta; Menlo Park (CA); Presencial; USD 178.000 - 250.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Bonus

Equity

Benefits

Descripción de la vacante

Meta is seeking an experienced ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP/SoC blocks, develop UVM-based test benches, and drive closure through coverage metrics, employing Formal and Emulation techniques as needed to reach a bug-free design.

You will work with cross-functional teams across design, model, emulation, and silicon validation to ensure first-pass silicon success for data-center applications.

Formación

• 8+ years of experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM or C/C++ based verification.
• Experience in leading verification of SoC/chiplet or complex IPs (PCIe, RoCE, DDR, HBM, Ethernet, Cache controllers, NoC).
• Proficiency with Python, TCL, Perl or Shell scripts used to build verification flows.

Responsabilidades

• Define and implement IP/SoC verification plans and build test benches for verification.
• Develop functional tests based on the verification plan and drive closure with metrics.
• Debug and root-cause functional failures in collaboration with the design team.
• Collaborate with cross-functional teams (Design, Model, Emulation, Silicon validation) to meet verification goals.
• Develop and drive continuous verification improvements using modern methodologies and tools.

Conocimientos

IP/SoC verification

SystemVerilog UVM

C/C++ verification

Python scripting

Verification planning

Herramientas

Git

Mercurial

EDA tools

Descripción del empleo

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Design Verification Engineer Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on the test plan, functional, and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications

• 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies and/or C/C++ based verification
• Experience in leading verification of SoC/chiplet or complex IP’s like PCIe, RoCE, DDR, HBM, Ethernet, Cache controllers, Network on Chip etc
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred Qualifications

• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
• Experience with verification of ARM/RISC-V based sub-systems or SoCs
• Experience working across and building relationships with cross-functional design, model and emulation teams
• Experience with micro-architectural performance verification
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Track record of 'first-pass success' in ASIC development cycles
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
• Experience verifying GPU/CPU designs
• Experience in development of UVM based verification environments from scratch

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Meta is proud to be an Equal Employment Opportunity and Aff... We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

Compensation

• $178,000/year to $250,000/year + bonus + equity + benefits
• Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable.
• In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.