ASIC Engineer, Implementation

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization in Sunnyvale is seeking a Staff ASIC Implementation Engineer to own end-to-end implementation from RTL to tape-out, driving synthesis, timing closure, and physical design in collaboration with RTL, verification, and architecture teams to deliver high-performance silicon at scale.

The role involves defining reusable flows, creating constraints, mentoring junior engineers, and advancing Meta's custom chip capabilities for AI, data center, and HPC

Qualifications

• 8+ years of experience in ASIC implementation including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs.
• Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Experience defining and managing synthesis constraints including SDC, UPF, and hierarchical design methodologies

Responsibilities

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects
• Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks through collaboration with RTL designers and physical design engineers
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles
• Generate SOC floorplans at the chip level, subsystem level, block level and enable block implementation owners to execute on synthesis & physical design
• Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimisation
• Partner with architecture and RTL teams to provide early feedback on design decisions that impact area, power, and timing outcomes
• Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out
• Identify and drive the resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders
• Mentor other engineers on implementation methodology, synthesis best practices, and timing analysis techniques
• Contribute to long-term silicon implementation strategy, evaluating new EDA tools, flows, and technologies to advance Meta's custom chip capabilities

Skills

ASIC implementation

Timing analysis

Scripting Tcl/Python

Synthesis flow design

Mentoring

Education

Bachelor's degree in Computer Science/Engineering or equivalent

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure behind Meta's AI, data center, and next-generation computing platforms. As a Staff ASIC Implementation Engineer, you will drive the physical implementation and synthesis of complex custom ASICs from RTL to tape-out, shaping the architectural and methodological decisions that define Meta's silicon roadmap. In this role, you will own end-to-end implementation flows, establish best practices across teams, and partner with design, verification, and physical design teams to deliver high-performance, power-efficient silicon at scale.

ASIC Engineer, Implementation Responsibilities:

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects
• Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks through collaboration with RTL designers and physical design engineers
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles
• Generate SOC floorplans at the chip level, subsystem level, block level and enable block implementation owners to execute on synthesis & physical design
• Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimisation
• Partner with architecture and RTL teams to provide early feedback on design decisions that impact area, power, and timing outcomes
• Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out
• Identify and drive the resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders
• Mentor other engineers on implementation methodology, synthesis best practices, and timing analysis techniques
• Contribute to long-term silicon implementation strategy, evaluating new EDA tools, flows, and technologies to advance Meta's custom chip capabilities

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in ASIC implementation, including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs
• Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus
• Experience defining and managing synthesis constraints including SDC, UPF, and hierarchical design methodologies
• Experience driving timing closure across multi-million gate designs with multiple clock domains and complex timing exceptions
• Experience developing and maintaining implementation automation using scripting languages such as Tcl or Python

Preferred Qualifications:

• Experience evaluating and integrating new EDA tools or methodologies into production implementation flows
• Familiarity with physical-aware synthesis and early floorplan co-design techniques to improve PPA outcomes
• Track record of defining implementation sign-off criteria and leading tape-out execution for complex ASIC designs
• Experience with custom ASIC implementation targeting data center, AI accelerator, or high-performance computing applications

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.