ASIC Engineer I: RTL/SoC Design for High-Scale Chips

Amazon; Cupertino (CA); On-site; USD 114,000 - 154,000; Full time

Benefits offered by this job

EAP

Mental Health Support

Medical Advice Line

401(k) matching

Job summary

Amazon's Annapurna Labs team seeks an ASIC Engineer I to contribute to RTL design, verification and physical design for ML accelerators and SoCs. You’ll collaborate across architectural, verification, and design teams and participate in silicon development from RTL through silicon.

Responsibilities include designing RTL in Verilog/SystemVerilog, building verification environments, and supporting timing and place-and-route. A degree in EE/CE/CS is required or preferred.

Qualifications

• Bachelor’s or Master’s degree in a relevant field is required or preferred.
• Experience with RTL design, verification and chip integration is expected.
• Familiarity with industry-standard EDA tools is a plus.

Responsibilities

• Designing and implementing RTL for digital logic blocks using Verilog/SystemVerilog.
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Skills

RTL design

Design verification

Physical design

SoC integration

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Cadence

Synopsys

Job description

Amazon's Annapurna Labs team seeks an ASIC Engineer I to contribute to RTL design, verification and physical design for ML accelerators and SoCs. You’ll collaborate across architectural, verification, and design teams and participate in silicon development from RTL through silicon.

Responsibilities include designing RTL in Verilog/SystemVerilog, building verification environments, and supporting timing and place-and-route. A degree in EE/CE/CS is required or preferred.