Trailblazing ASIC Design Engineer II

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Job summary

Annapurna Labs (U.S.) Inc. seeks an ASIC Design Engineer to drive high-performance, power-efficient RTL designs for AWS inference servers.

You will create SystemVerilog RTL, analyze architectures, and collaborate with cross-functional teams to ensure design quality and timely delivery. The role requires a strong ASIC design background, proficiency in SystemVerilog, and excellent analytical and problem-solving skills.

Qualifications

• Bachelor's degree or equivalent required.
• 3+ years of non-internship design or architecture experience on new and existing systems.
• Strong background in ASIC design and SystemVerilog knowledge.

Responsibilities

• Develop high-performance RTL designs that are area- and power-efficient.
• Analyze designs, microarchitectures, and architectures to optimize trade-offs.
• Create microarchitectures, implement SystemVerilog RTL, and deliver timing-clean designs.

Skills

SystemVerilog

RTL design

Clock domain crossing

Performance optimization

Education

Bachelor's degree or equivalent

Master's degree in CS or related field

Tools

SystemVerilog

Job description

Annapurna Labs (U.S.) Inc. seeks an ASIC Design Engineer to drive high-performance, power-efficient RTL designs for AWS inference servers.

You will create SystemVerilog RTL, analyze architectures, and collaborate with cross-functional teams to ensure design quality and timely delivery. The role requires a strong ASIC design background, proficiency in SystemVerilog, and excellent analytical and problem-solving skills.