ASIC Engineer I Internship: RTL, Verification & SoC

Amazon; Seattle (WA); On-site; USD 116,000 - 134,000; Full time

Job summary

Amazon – Annapurna Labs ASIC internship in Seattle, Austin or Cupertino – seeks an ASIC Engineer I intern to contribute to real chip development. You will work on RTL design, verification and collaboration with cross-functional teams to translate specifications into silicon.

Ideal candidates have degrees in EE/CE/CS, digital design coursework, and familiarity with Verilog/SystemVerilog; internship offers hands-on learning and potential future opportunities in ASIC design.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Coursework or project experience in digital logic design and computer architecture
• Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL)
• Understanding of fundamental digital design concepts: combinational and sequential logic, finite state machines, timing, and clocking

Responsibilities

• Designing and implementing RTL for digital logic blocks using Verilog/SystemVerilog
• Developing and running verification environments to validate design functionality and coverage
• Supporting synthesis, timing analysis, and physical design flows
• Debugging design issues through simulation and analysis
• Collaborating with architecture, verification, and physical design teams to take features from specification to silicon
• Documenting your design decisions and presenting your work to the team

Job description

Amazon – Annapurna Labs ASIC internship in Seattle, Austin or Cupertino – seeks an ASIC Engineer I intern to contribute to real chip development. You will work on RTL design, verification and collaboration with cross-functional teams to translate specifications into silicon.

Ideal candidates have degrees in EE/CE/CS, digital design coursework, and familiarity with Verilog/SystemVerilog; internship offers hands-on learning and potential future opportunities in ASIC design.