ASIC Engineer I — Silicon Design & Verification Intern

Amazon Inc.; Seattle, Northern (WA, KY); Hybrid; USD 99,000 - 134,000; Full time

Job summary

Amazon is offering an ASIC Engineer I internship featuring hands-on work in RTL design, verification, and chip development for Graviton, Trainium, Inferentia, and Nitro stack. You will design RTL in Verilog/SystemVerilog, develop verification environments, and collaborate across teams to turn features into silicon.

Eligible students in EE/CE/CS graduating by May 2027 or earlier, with coursework in digital logic and computer architecture, and HDL familiarity, will gain real responsibility from

Qualifications

• Bachelor's or Master's degree in EE/CE/CS with graduation by May 2027
• Coursework or project experience in digital logic design and computer architecture
• Familiarity with Verilog/SystemVerilog/VHDL
• Understanding of digital design concepts: combinational and sequential logic, FSMs, timing, clocking

Responsibilities

• Design RTL for digital logic blocks using Verilog/SystemVerilog
• Develop and run verification environments to validate design functionality and coverage
• Supporting synthesis, timing analysis, and physical design flows
• Debugging design issues through simulation and analysis
• Collaborating with architecture, verification, and physical design teams to take features from specification to silicon
• Documenting your design decisions and presenting your work to the team

Skills

Digital logic design

Computer architecture

Verilog/SystemVerilog/VHDL

Digital design concepts

Education

Bachelor's or Master's degree in Electrical Engineering/Computer Engineering/Computer Science, graduation by May 2027 or earlier

Graduation by May 2027 or earlier

Tools

Cadence

Synopsys

Job description

Amazon is offering an ASIC Engineer I internship featuring hands-on work in RTL design, verification, and chip development for Graviton, Trainium, Inferentia, and Nitro stack. You will design RTL in Verilog/SystemVerilog, develop verification environments, and collaborate across teams to turn features into silicon.

Eligible students in EE/CE/CS graduating by May 2027 or earlier, with coursework in digital logic and computer architecture, and HDL familiarity, will gain real responsibility from