ASIC Engineer, Design

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Meta in Sunnyvale, CA is hiring ASIC Design Engineers to build cutting-edge chips for ML, video transcoding, and network acceleration. You will own architecture exploration, micro-architecture development, and IP identification and integration with verification and emulation teams.

You will collaborate with implementation to meet timing and power targets, work with Synthesis, Timing Closure, and Formal Verification methodologies, and contribute to a world-class hardware team in a fast-paced

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration.
• Micro-architecture development for complex IPs.
• Soft and hard IP identification, selection and integration.
• Collaborate with verification and emulation teams in test plan development and debug.
• Collaborate with implementation team to close the design on timing and power.

Skills

Architecture exploration

Micro-architecture development

IP identification

IP selection

IP integration

Test plan development

Collaboration

Education

Bachelor's degree in CS/CE or equivalent

Tools

Verilog

SystemVerilog

HLS

Job description

# ASIC Engineer, DesignSunnyvale, CA+1 locationHardware+ 2 moreApply nowMeta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.---## ASIC Engineer, Design Responsibilities* Architecture exploration* Micro-architecture development* Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug* Collaboration with implementation team to close the design on timing and power## Minimum Qualifications* Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience* 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration* RTL development using Verilog, System Verilog and HLS## Preferred Qualifications* Experience in CPU, NOC, Memory and Peripheral Subsystems* Experience with Synthesis, Timing Closure and Formal Verification Methodology* Master’s or PhD degree in Electrical Engineering, Computer Science or related areas