Senior ASIC Design Engineer

Themesoft Inc.; Mountain View (CA); Hybrid; USD 180,000 - 230,000; Full time

Job summary

Themesoft Inc. is seeking an experienced senior digital designer to craft high-performance NoC IP for AI SoCs in Mountain View.

You will define microarchitecture and deliver synthesizable RTL (Verilog/SystemVerilog), ensuring tight timing, CDC/Lint closure, and PPA optimization across the design stack. You will collaborate with architecture, verification, physical design, and SoC integration teams while also writing Python scripts to automate design flows and boost productivity in a highly

Qualifications

• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.

Responsibilities

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Skills

ASIC

NoC

RTL

SystemVerilog

Microarchitecture

CDC

Lint

Synthesis

Timing

PPA

Python

Tools

Verilog

SystemVerilog

Job description

Location: Mountain View CA (onsite - Hybrid)

Job Type: FullTime.

Responsibilities

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Qualifications

• 6+ years of hands‑on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade‑offs.
• Experience with NoC/interconnect and high‑throughput/low‑latency designs.
• Experience with SoC integration, post‑silicon debug, and Python scripting.

Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python

Work Authorization:

Applicants must be legally authorized to work in the United States.

Themesoft Inc is an Equal Employment Opportunity employer. We consider qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other status protected by applicable federal, state, or local law.