ASIC DFT Engineer II - Design-for-Test Innovator

Cisco; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Cisco's Silicon One team is developing innovative ASIC platforms powering switching, routing, and wireless products worldwide. The ASIC Design for Test Engineer focuses on design-for-testability early in the design cycle.

You will work with frontend RTL and backend Physical Design teams to drive DFT requirements, implement test features, and validate test timing across the flow, using SystemVerilog and ATPG tools.

Qualifications

• Master's degree with 0 years of work experience or Bachelor's degree with 2 years of work experience in ASIC Eng or related field.
• Foundational understanding of JTAG, scan architectures, and BIST (memory BIST and boundary scan).
• Familiarity with EDA and ATPG tools and scripting or coding in Python, Tcl, or Perl.
• Experience with gate-level simulations and debugging using simulators like VCS.

Responsibilities

• Implement the Hardware Design-for-Test (DFT) features for ATE, in-system test, debug and diagnostics.
• Create and enhance automation scripts to improve implementation robustness and efficiency.
• Collaborate with frontend RTL, backend Physical Design, and verification teams to integrate and validate Test logic across implementation and post-silicon validation flows.
• Validate test timing and logic equivalency using SystemVerilog.

Skills

Verbal and written communication

Collaboration

Problem solving

Education

Master's degree in Electrical Engineering or related field

Bachelor's degree in ASIC Engineering or related field

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco's Silicon One team is developing innovative ASIC platforms powering switching, routing, and wireless products worldwide. The ASIC Design for Test Engineer focuses on design-for-testability early in the design cycle.

You will work with frontend RTL and backend Physical Design teams to drive DFT requirements, implement test features, and validate test timing across the flow, using SystemVerilog and ATPG tools.