ASIC Design Verification Engineer, Digital Signal Processing

Anysilicon; Sunnyvale (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Google is seeking an ASIC Design Verification Engineer, Digital Signal Processing, to contribute to Tensor Processing Unit development within the AI and Infrastructure team. You will define verification strategies for high-speed PHY blocks and verify RTL against reference models using SystemVerilog-AMS, SystemC, and MATLAB.

The role requires a bachelor’s in electrical or computer engineering and 8 years of DSP verification experience, with strong Python/MATLAB/C/C++ testbench skills and

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 8 years of design verification experience in DSP, communications, or arithmetic logic blocks.
• Proficiency in Python, MATLAB, or C/C++ for testbench automation.

Responsibilities

• Define and execute verification strategies for high-speed PHY digital blocks.
• Verify RTL against architectural reference models using MATLAB, C++, or SystemC.
• Assess stability of adaptive equalization loops and timing recovery under channel impairments.
• Model and verify the interface between Digital DSP blocks and Analog Front End using Real Number Modeling or SV-AMS.
• Design and maintain scalable UVM-based simulation environments, SystemVerilog Assertions, and coverage metrics.

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

SystemVerilog-AMS

SystemC

MATLAB

Python

C/C++

UVM

Job description

ASIC Design Verification Engineer, Digital Signal Processing

Join Google's AI and Infrastructure team as a Design Verification Engineer, focusing on the cutting-edge development of Tensor Processing Units (TPUs) that power AI/ML applications. This role involves shaping the future of hardware acceleration through innovative silicon solutions, contributing to products that impact millions globally.

Responsibilities:

• Define and execute verification strategies for high-speed Physical Layer (PHY) digital blocks.
• Verify RTL implementations against high-level architectural reference models using methodologies like MATLAB, C++, or SystemC.
• Assess the stability, tracking capability, and convergence of adaptive equalization loops and timing recovery systems under various channel impairments.
• Model and verify the functional interface between Digital DSP blocks and the Analog Front End using Real Number Modeling or SystemVerilog-AMS.
• Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions, and functional coverage metrics for digital signal processing blocks.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8 years of experience in design verification with a focus on digital signal processing, communication systems, or arithmetic logic blocks.

Skills:

• Experience with scripting in Python, Perl, or Makefile for automation.
• Functional knowledge of adaptive equalization architectures and timing recovery loops.
• Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.