ASIC Design Verification Engineer, Machine Learning

Google; Sunnyvale (CA); On-site; USD 127,000 - 187,000; Full time

Job summary

Google is seeking an ASIC Design Verification Engineer for ML workloads in Sunnyvale, CA. You will shape AI/ML hardware acceleration by evaluating TPU architecture and verifying complex digital designs, contributing to high-performance silicon for Google's AI products.

You will collaborate with design and software teams to ensure correct functionality, scalability, and integration of verification environments and test plans.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• At least 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with SystemVerilog (e.g., SystemVerilog Assertions or functional coverage).

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

SystemVerilog

UVM

RTL verification

Constrained-random verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

SVA

Formal verification tools

Power aware verification

Job description

ASIC Design Verification Engineer, Machine Learning

Google

Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with SystemVerilog (e.g., SystemVerilog Assertions or functional coverage).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 4 years of experience in design verification.
• Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
• Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).
• Familiarity with ASIC standard interfaces and memory system architecture.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.