ASIC Design Engineer – SystemVerilog RTL for High Perf HW

Amazon; Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA is hiring for an ASIC II to design and optimize hardware in data centers, including AWS Inferentia. You will develop high-performance RTL designs and SystemVerilog implementations to meet strict power and area targets.

Responsibilities include linting and timing checks, collaborating with architects, verification teams, and back-end experts. Requires a Bachelor's in CS/Engineering and 3 years of relevant experience.

Qualifications

• Bachelor's degree in CS, Engineering, or a related field with 3 years of relevant design/architecture experience.
• 3 years of design/architecture experience for new and existing systems.
• 3 years of experience with Micro-Architecture, SystemVerilog and RTL design; familiarity with code quality tools (Spyglass, LINT, CDC).

Responsibilities

• Design and optimize hardware in data centers including AWS Inferentia.
• Create high-performance, area- and power-efficient RTL designs meeting project targets.
• Collaborate with architects, verification, and back-end teams to ensure design integrity.

Skills

RTL design

Micro-architecture

SystemVerilog

Collaboration

Education

Bachelor's degree in Computer Science or Engineering

Tools

SystemVerilog

RTL design

Spyglass

LINT

CDC

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA is hiring for an ASIC II to design and optimize hardware in data centers, including AWS Inferentia. You will develop high-performance RTL designs and SystemVerilog implementations to meet strict power and area targets.

Responsibilities include linting and timing checks, collaborating with architects, verification teams, and back-end experts. Requires a Bachelor's in CS/Engineering and 3 years of relevant experience.