Senior ASIC RTL Designer – Microarchitecture & SystemVerilog

Amazon Inc.; Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA, is hiring for an ASIC II role (AMZ27538.3) to design and optimize hardware for cloud infrastructures, including AWS Inferentia.

The position runs 40 hours per week, 8:00am-5:00pm, with a salary range of $157,300–$212,800; base pay varies by experience and market location. The ideal candidate holds a bachelor's degree in CS or engineering and 3+ years in design/architecture, SystemVerilog RTL, and code-quality tools.

Qualifications

• Bachelor's degree or foreign equivalent in Computer Science, Engineering, or a related discipline.
• 3 years of design or architecture experience.
• 3 years of SystemVerilog/RTL design experience.
• 3 years of experience with code quality tools including Spyglass, LINT or CDC.

Responsibilities

• Help provide a highly reliable, scalable, low-cost infrastructure platform in the cloud.
• Design and optimize hardware in data centers including AWS Inferentia.
• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Execute lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate with architects, designers, verification and back-end teams to deliver silicon.

Skills

Micro-Architecture

SystemVerilog RTL

Code quality tools

Education

Bachelor's degree in Computer Science or Engineering

Tools

Spyglass

LINT

CDC

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA, is hiring for an ASIC II role (AMZ27538.3) to design and optimize hardware for cloud infrastructures, including AWS Inferentia.

The position runs 40 hours per week, 8:00am-5:00pm, with a salary range of $157,300–$212,800; base pay varies by experience and market location. The ideal candidate holds a bachelor's degree in CS or engineering and 3+ years in design/architecture, SystemVerilog RTL, and code-quality tools.