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Marvell seeks a master’s student in MSEE or MSCE to design and verify test chip experiments using Verilog simulation, and to develop Verilog-based test patterns for hardware validation.
You will create software tools in Perl, Python, and Tcl for design support, hardware characterization, data processing, and results analysis, and work in Linux/Unix environments.
Expected graduation Fall 2027 to Summer 2028; strong teamwork and export-control information eligibility required.
Design and verify test chip experiments using Verilog simulation
Develop, generate, simulate, and debug Verilog-based test patterns for hardware validation of test chip experiments
Develop and maintain laboratory environments supporting hardware debug, diagnostics, characterization, and measurement data collection
Create software tools and automation scripts in Perl, Python, and Tcl for design support, hardware characterization, laboratory measurements, data processing, and results analysis
Analyze, summarize, document, and present characterization and validation results to engineering teams and stakeholders
Provide hardware validation for custom SRAM, logic, I/O, and security circuits across Marvell business units in advanced semiconductor technology nodes
Demonstrates expertise in Verilog simulation and hardware validation, with strong programming skills in Perl and Python for automation and data analysis. Proficient in digital logic circuits and semiconductor device physics, capable of collaborating effectively in multidisciplinary teams.