Physical Design Engineer Intern

Jobtailor; California (MO); On-site; USD 34,000 - 48,000; Full time

Job summary

Jobtailor is seeking an engineering intern to support VLSI design activities, focusing on synthesis, place-and-route, and timing closure. You will write scripts in Python and TCL to automate CAD workflows and debug design issues with CAD tools in a Unix environment.

Ideal candidates will have coursework in VLSI, Verilog/SystemVerilog, and timing analysis, with strong problem-solving and communication skills and eligibility for export-controlled information reviews.

Qualifications

• Enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field
• Expected graduation date Fall 2027 to Summer 2028
• Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog/SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
• Proficiency in Python, TCL, Perl, and Shell
• Experience working in a Unix-type environment
• Experience using Synopsys PrimeTime, Cadence Tempus, and Mentor
• Strong analysis, problem-solving, and communication skills
• Applicants must be eligible to access export-controlled information under applicable law; some applicants may be subject to an export license review process prior to employment

Responsibilities

• Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry-standard EDA tools
• Write Python, TCL, Perl, and Shell scripts to support design and development activities
• Analyze, debug, and implement fixes for design violations using CAD tools
• Collaborate with RTL, synthesis, and other design teams to resolve congestion and timing bottlenecks
• Ensure designs converge and integrate in a timely manner

Skills

VLSI Design

Timing Analysis

Python Programming

Verilog/SystemVerilog

Digital Logic

Circuit Design

Analysis

Communication

Education

Bachelor's Degree in Electrical/Computer Engineering

Tools

Synthesis Tools

Place And Route

Clock Insertion

Static Timing Analysis

Mentor

Synopsys PrimeTime

Cadence Tempus

Unix Environment

Job description

• Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry-standard EDA tools
• Write Python, TCL, Perl, and Shell scripts to support design and development activities
• Analyze, debug, and implement fixes for design violations using CAD tools
• Collaborate with RTL, synthesis, and other design teams to resolve congestion and timing bottlenecks
• Ensure designs converge and integrate in a timely manner

Requirements

• Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field
• Expected graduation date between Fall 2027 and Summer 2028
• Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
• Proficiency in Python, TCL, Perl, and Shell
• Experience working in a Unix-type environment
• Experience using Synopsys PrimeTime, Cadence Tempus, and Mentor
• Strong analysis, problem-solving, and communication skills
• Applicants must be eligible to access export-controlled information under applicable law; some applicants may be subject to an export license review process prior to employment

Core Competencies

Proficient in VLSI design methodologies, including synthesis, place and route, and timing analysis, with strong programming skills in Python, TCL, Perl, and Shell. Capable of collaborating effectively with design teams to resolve technical challenges and ensure timely project delivery.

Highest-signal resume keywords

• VLSI Design
• Timing Analysis
• Python Programming
• Synopsys PrimeTime
• Cadence Tempus

ATS Optimization Keywords

Hard Skills

• Synthesis
• Place And Route
• Clock Insertion
• Timing Closure
• Static Timing Analysis
• Verilog
• SystemVerilog
• Digital Logic
• Circuit Design
• Microelectronics

Soft Skills

• Analysis
• Problem-Solving
• Communication

Industry Keywords

• Export-Controlled Information
• Congestion Resolution
• Timing Bottlenecks
• Design Violations

Tools & Technologies

• EDA Tools
• CAD Tools
• Unix Environment
• Mentor