Analog Design Intern: Verilog Validation & Lab Automation

Jobtailor; California (MO); On-site; USD 55,000 - 83,000; Part time

Job summary

Marvell seeks a master’s student in MSEE or MSCE to design and verify test chip experiments using Verilog simulation, and to develop Verilog-based test patterns for hardware validation.

You will create software tools in Perl, Python, and Tcl for design support, hardware characterization, data processing, and results analysis, and work in Linux/Unix environments.

Expected graduation Fall 2027 to Summer 2028; strong teamwork and export-control information eligibility required.

Qualifications

• Enrolled in a Master’s program in MSEE, MSCE or related field.
• Expected graduation Fall 2027 - Summer 2028.
• Strong understanding of digital logic circuits, memory architectures, I/O circuits, and semiconductor device physics.
• Proven experience in design and development.
• Proficiency in Linux/Unix environments.
• Excellent communication skills (verbal and written).
• Export-controlled information eligibility as defined by law.

Responsibilities

• Design and verify test chip experiments using Verilog simulation.
• Develop, generate, simulate, and debug Verilog-based test patterns for hardware validation.
• Develop and maintain lab environments supporting hardware debug, diagnostics, characterization, and data collection.
• Create software tools and automation scripts in Perl, Python, and Tcl for design support, hardware characterization, data processing, and results analysis.
• Analyze, summarize, document, and present characterization and validation results to engineering teams.
• Provide hardware validation for SRAM, logic, I/O, and security circuits across Marvell units in advanced semiconductor nodes.

Skills

Verilog Simulation

Hardware Validation

Digital Logic Circuits

Memory Architectures

I/O Circuits

Semiconductor Device Physics

Linux/Unix Proficiency

Automation Scripting

Data Processing

Results Analysis

Education

Master's Degree in MSEE

Master's Degree in MSCE

Tools

Perl

Python

Tcl

Job description

Marvell seeks a master’s student in MSEE or MSCE to design and verify test chip experiments using Verilog simulation, and to develop Verilog-based test patterns for hardware validation.

You will create software tools in Perl, Python, and Tcl for design support, hardware characterization, data processing, and results analysis, and work in Linux/Unix environments.

Expected graduation Fall 2027 to Summer 2028; strong teamwork and export-control information eligibility required.