Design Verification Intern

Jobtailor; California (MO); Hybrid; USD 28,000 - 48,000; Full time

Job summary

Jobtailor is seeking a Master’s student to explore processor architecture and simulation environments, analyzing how advanced processors operate and how RTL integrates with SoC/ASIC components.

You will develop automated tests, push designs to limits, and analyze coverage while collaborating with chip architects and cross-functional teams to drive product innovations.

Qualifications

• Master's degree in Electrical/Computer Engineering or related field
• Expected graduation Fall 2027 to Summer 2028
• Courses focusing on architecture, Verilog, VLSI, UVM, SoC/ASIC design, verification principles
• Proficiency in programming languages such as Python, C, C++, Perl, and Java
• Experience with tools such as Synopsys, Cadence, or Mentor for simulations and testbenches
• Hands-on RTL integration and bring-up system
• Experience debugging complex hardware/software interactions
• Eligible to access export-controlled information under U.S. law

Responsibilities

• Dive deep into processor architecture and learn how processors function
• Use industry-standard tools to create simulation environments that mimic real-world conditions
• Develop automated tests that push designs to their limits and identify hidden flaws and failed simulations
• Analyze test coverage results and metrics
• Collaborate with chip architects, designers, and cross-functional partners to solve complex problems and contribute to products

Skills

Python

C

C++

Perl

Java

Problem solving

Communication

Education

Master's Degree in Electrical Engineering

Tools

Synopsys

Cadence

Mentor graphics

Job description

• Dive deep into the architecture of cutting-edge processors and learn how they function
• Use industry-standard tools to create simulation environments that mimic real-world conditions
• Develop automated tests that push designs to their limits and identify hidden flaws and failed simulations
• Analyze test coverage results and metrics
• Collaborate with chip architects, designers, and cross-functional partners to solve complex problems and contribute to products

Requirements

• Currently enrolled in a Master's Degree in Electrical Engineering, Computer Engineering, or a related field
• Expected graduation date between Fall 2027 and Summer 2028
• Completed courses focusing on computer architecture, logic, processor, memory system, Verilog, VLSI, VHDL, UVM, analog, integrated circuit design, digital logic design, SoC/ASIC design, verification principles, signals, system and signal processing
• Proficiency in programming and scripting languages such as Python, C, C++, Perl, and Java
• Experience using tools such as Synopsys, Cadence, or Mentor to run simulations and write and debug a testbench
• Hands-on experience with RTL integration and bring-up system
• Experience debugging complex hardware/software interactions
• Strong analysis, problem-solving, and communication skills
• Applicants must be eligible to access export-controlled information under applicable U.S. law; some applicants may be subject to an export license review process

Core Competencies

Demonstrates expertise in processor architecture and simulation environments, with proficiency in programming languages and tools essential for testing and debugging complex hardware/software interactions. Strong analytical and problem-solving capabilities are crucial for collaborating with cross-functional teams in the development of cutting-edge products.

Highest-signal resume keywords

• Master's Degree In Electrical Engineering
• Proficiency In Python, C, C++, Perl, Java
• Experience With Synopsys, Cadence, Mentor
• Hands-On Experience With RTL Integration
• Strong Analysis And Problem-Solving Skills

Hard Skills

• Computer Architecture
• Logic Design
• Processor Design
• Memory System Design
• Verilog
• VLSI
• VHDL
• UVM
• Digital Logic Design
• SoC/ASIC Design

Soft Skills

• Strong Communication Skills

Industry Keywords

• Export-Controlled Information
• Integrated Circuit Design
• Verification Principles
• Signals
• System And Signal Processing

Tools & Technologies

• Simulation Environments
• Testbench Debugging