Mixed Signal Verification Engineer

5 Star Recruitment; Austin (TX); On-site; USD 110,000 - 130,000; Full time

Job summary

A leading recruitment agency in the U.S. is seeking a Mixed Signal Verification Engineer with over 5 years of experience in behavioral modeling of analog design and proficiency in Verilog/SystemVerilog coding. The role requires familiarity with verification methodologies and the ability to develop scalable test cases in a collaborative team environment. Candidates with experience in UVM and various industry-standard tools are preferred. The company offers visa sponsorship for H1-B applicants.

Qualifications

• 5+ years of total experience in Analog design verification.
• Experience in Verilog/SystemVerilog coding.
• Familiarity with verification methodologies and tools including simulators.

Responsibilities

• Verify Analog/mixed-signal designs in a collaborative team environment.
• Develop scalable and portable test cases.
• Write test plans and present results to multi-functional teams.

Skills

Behavioral Modelling (BM) of Analog design

Verilog/SystemVerilog coding

Virtuoso Schematics tools

Verification Methodologies and Tools

UVM

Strong communication skills

Tools

Synopsys

Cadence tools

Job description

About the job Mixed Signal Verification Engineer

Requirements

Minimum Qualifications

• 5+ years of total experience
• Experience in Behavioural Modelling (BM) of Analog design for digital verification
• Experience in Verilog/SystemVerilog coding
• Experience in Virtuoso Schematics tools
• Basic knowledge in Analog design

Preferred Qualifications

• Experience in UVM
• Experience in both Synopsys and Cadence tools is an advantage

Additional Skills

• Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
• Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
• Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Required Citizenship / Work Permit / Visa Status*
Will sponsor H1-B

Must-Haves
5+ years of total experience
Experience in Behavioural Modelling (BM) of Analog design for digital verification
Experience in Verilog/System Verilog coding
Experience in Virtuoso Schematics tools
Experience in UVM
Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.