Mixed Signal Verification Engineer

Retym, Inc; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

Retym, Inc is seeking a Mixed Signal Verification Engineer to develop cutting-edge technology for high-speed communication. The ideal candidate will have over 5 years of experience in mixed signal verification, including proficiency in Verilog/SystemVerilog coding and behavioural modelling of analog designs.

Key responsibilities include developing verification strategies, creating behavioural models, and writing testbenches. Strong communication skills and the ability to work in a collaborative environment are essential.

Qualifications

• 5+ years of experience in mixed signal verification.
• Proficiency in Verilog/SystemVerilog coding.
• Basic knowledge in analog design.

Responsibilities

• Develop verification strategies for mixed signal designs.
• Create behavioural models for analog blocks.
• Write and debug testbenches using UVM methodology.

Skills

Behavioural Modelling (BM)

Mixed Signals dynamic Verification

Verilog/SystemVerilog coding

Verification Methodologies and Tools

Collaboration in a team environment

Strong communication skills

Tools

AMS tools

Virtuoso Schematics

Synopsys tools

Cadence tools

Job description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer.

Key Responsibilities

• Develop verification strategies for digital and analog (mixed‑signal) designs, utilizing UVM methodologies based on specifications.
• Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
• Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed‑signal blocks.
• Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
• Perform and troubleshoot unit‑level, cluster‑level and top‑level simulations of mixed‑signal designs.

Minimum Qualifications

• 5+ years of experience
• Experience in Behavioural Modelling (BM) of Analog design for digital verification
• Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
• Experience in Verilog/SystemVerilog coding
• Experience in Virtuoso Schematics tools
• Basic knowledge in Analog design

Preferred Qualifications

• Experience in UVM
• Experience in both Synopsys and Cadence tools is an advantage

Additional Skills

• Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
• Collaborative Environment: Ability to verify Analog/mixed‑signal designs in a collaborative team environment.
• Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi‑functional teams.