AI Memory Architect — HBM & System Infrastructure

Micron Technology; Nebraska; On-site; USD 110,000 - 170,000; Full time

Job summary

Micron Technology is seeking an AI Infrastructure & HBM Architecture Engineer to explore next-generation AI memory and system environments. You will analyze infrastructure trends, contribute to performance modeling, and support tools for informing HBM architecture decisions.

You will collaborate with senior engineers across DTPCO, Design, and Product/System teams to understand how AI workloads influence memory system design and architectural intercept strategies.

Qualifications

• Currently pursuing a Master’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong foundation in computer architecture, digital systems, and hardware/software interaction.
• Interest in memory subsystem design (HBM, DDR, caches) and how it impacts AI/ML workloads.
• Deep understanding of LLM pipeline and critical bottlenecks.
• Programming experience in Python, C/C++, or similar languages.

Responsibilities

• Research emerging trends in compute, networking, and storage infrastructure to anticipate future AI workloads.
• Support HBM architecture analysis by collecting and synthesizing data on bandwidth, latency, and memory requirements.
• Help develop or refine simulation frameworks to model AI cluster performance and memory subsystem behavior.
• Assist in building first-order performance models for HBM bandwidth, latency, GPU/CPU interactions, and memory hierarchy trade-offs.
• Participate in building trend dashboards using CSP benchmarks and industry datasets.
• Collaborate with DTPCO mentors to explore architectural intercept opportunities for next-generation AI systems.

Skills

Python

C/C++

Computer architecture

LLM pipeline

Education

Master’s or PhD in E.E./C.E./C.S.

Job description

Micron Technology is seeking an AI Infrastructure & HBM Architecture Engineer to explore next-generation AI memory and system environments. You will analyze infrastructure trends, contribute to performance modeling, and support tools for informing HBM architecture decisions.

You will collaborate with senior engineers across DTPCO, Design, and Product/System teams to understand how AI workloads influence memory system design and architectural intercept strategies.