AI Hardware Design Engineer

Persimmons, Inc.; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive salary package

Flexible PTO

401k

Job summary

Persimmons, Inc. in San Jose, CA, seeks a Silicon Design Engineer to deliver high‑quality RTL drops to PD partners and drive SoC implementation from RTL to tape‑out.

You will collaborate with architecture, software, and design teams to meet performance, power, and area targets, while building automated design flows and leveraging AI tools to accelerate iterations. You will bring 3+ years in RTL-to-PD work, strong SystemVerilog skills, and experience with Cadence or Synopsys toolchains.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• 3+ years of hands-on RTL-to-PD implementation experience, with success taking designs from synthesis through tape-out on real silicon
• MAS, test plan development, test implementation, and debugging across IP blocks, SoCs, and system-level designs
• Strong SystemVerilog, verification methodology, and C/C++ embedded code for processors validation
• Proficiency in SystemVerilog/Verilog and Cadence and/or Synopsys toolchains with quality and sign-off checks
• Strong command of static timing analysis and ability to write timing constraints from RTL-level design
• Experience developing scripted, automated design flows; exposure to AI-assisted automation tools is a plus
• Fluency with modern AI tools and workflows for research, analysis, or productivity

Responsibilities

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, UPF and static checks
• Lead unit level design execution and verification planning with architecture, software, and design teams to meet SoC specs
• Drive timing closure by authoring precise timing constraints from RTL, running static timing analysis, and resolving setup violations
• Execute floorplanning and physical implementation using Cadence/Synopsys tools to optimize PPA
• Build and maintain scripted, automated design flows to accelerate synthesis, analysis, and sign-off
• Collaborate with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs and quality checks
• Contribute to post-DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and MBIST integration

Skills

SystemVerilog

RTL design

Verification methodology

C/C++ embedded

Timing constraints

Synthesis tools

AI tooling familiarity

Cadence tools

Synopsys tools

Team collaboration

Education

Bachelor’s or Master’s degree in Electrical or Computer Engineering

Tools

Cadence tools

Synopsys tools

Synthesis toolchains

Job description

Persimmons, Inc. in San Jose, CA, seeks a Silicon Design Engineer to deliver high‑quality RTL drops to PD partners and drive SoC implementation from RTL to tape‑out.

You will collaborate with architecture, software, and design teams to meet performance, power, and area targets, while building automated design flows and leveraging AI tools to accelerate iterations. You will bring 3+ years in RTL-to-PD work, strong SystemVerilog skills, and experience with Cadence or Synopsys toolchains.