Silicon Design Engineer

Persimmons, Inc.; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive salary package

Flexible PTO

401k

Job summary

Persimmons, Inc. in San Jose, CA, seeks a Silicon Design Engineer to deliver high‑quality RTL drops to PD partners and drive SoC implementation from RTL to tape‑out.

You will collaborate with architecture, software, and design teams to meet performance, power, and area targets, while building automated design flows and leveraging AI tools to accelerate iterations. You will bring 3+ years in RTL-to-PD work, strong SystemVerilog skills, and experience with Cadence or Synopsys toolchains.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• 3+ years of hands-on RTL-to-PD implementation experience, with success taking designs from synthesis through tape-out on real silicon
• MAS, test plan development, test implementation, and debugging across IP blocks, SoCs, and system-level designs
• Strong SystemVerilog, verification methodology, and C/C++ embedded code for processors validation
• Proficiency in SystemVerilog/Verilog and Cadence and/or Synopsys toolchains with quality and sign-off checks
• Strong command of static timing analysis and ability to write timing constraints from RTL-level design
• Experience developing scripted, automated design flows; exposure to AI-assisted automation tools is a plus
• Fluency with modern AI tools and workflows for research, analysis, or productivity

Responsibilities

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, UPF and static checks
• Lead unit level design execution and verification planning with architecture, software, and design teams to meet SoC specs
• Drive timing closure by authoring precise timing constraints from RTL, running static timing analysis, and resolving setup violations
• Execute floorplanning and physical implementation using Cadence/Synopsys tools to optimize PPA
• Build and maintain scripted, automated design flows to accelerate synthesis, analysis, and sign-off
• Collaborate with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs and quality checks
• Contribute to post-DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and MBIST integration

Skills

SystemVerilog

RTL design

Verification methodology

C/C++ embedded

Timing constraints

Synthesis tools

AI tooling familiarity

Cadence tools

Synopsys tools

Team collaboration

Education

Bachelor’s or Master’s degree in Electrical or Computer Engineering

Tools

Cadence tools

Synopsys tools

Synthesis toolchains

Job description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.

Why join us:

We’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you’re ready to join a world‑class team and play a critical role in making a global impact ‑ we want to talk to you.

What you’ll do:

As a Persimmons Silicon Design Engineer, you will be responsible for high quality RTL drops to our PD Partners of next‑generation AI silicon. Your primary duties and responsibilities include:

• Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets
• Lead unit level design execution & verification planning. Collaborate with architecture, software, and design teams to develop MAS, execution & test plans that ensures we meet SoC specifications
• Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi‑corner environments
• Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA
• Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign‑off processes - leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead
• Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy
• Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands

Requirements

What You Bring To The Table:

• Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• Proven Experience: 3+ years of hands‑on RTL‑to‑PD implementation experience, with demonstrated success taking designs from synthesis through tape‑out on real silicon
• Experience with MAS & test plan development, test implementation, and complex debugging across diverse IP blocks, SoCs, and system‑level designs
• Strong skills in SystemVerilog, Verification methodology, and C/C++ embedded code for processors validation
• Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign‑off checks
• Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL‑level design understanding
• Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI‑assisted automation tools is a strong plus
• Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity)

Benefits

• Competitive salary and benefits package
• Flexible PTO
• 401k