AI Accelerator Design Verification Engineer - Full Time

RosaicLabs Inc; Austin (TX); Presencial; USD 120.000 - 160.000; Tempo integral

Benefícios oferecidos por esta vaga

Medical (including HSA)

Dental

Vision

Life & AD&D

401(k)

Resumo da vaga

RosaicLabs Inc is seeking an AI Accelerator Design Verification Engineer to own verification environments for AI chips, from test plans to coverage closure and SI bring-up. You will develop verification plans and write SystemVerilog/UVM testbenches, plus build emulation-friendly benches for sim and FPGA prototypes.

You will verify datapaths against bit-accurate models, run ML kernels, and collaborate with RTL/design teams to drive bugs to closure while using formal verification where

Qualificações

• Bachelor's or Master's in Electrical/Computer Engineering, CS or related field.
• Strong background in AI accelerator design and computer architecture.
• Experience with SystemVerilog/UVM and modern verification flows.
• Familiarity with emulation, FPGA prototyping, and coverage concepts.

Responsabilidades

• Develop verification plans for AI accelerator blocks and SoC flows.
• Write and debug SystemVerilog/UVM testbenches, checkers, and scoreboards.
• Build emulation-friendly testbenches for sim and emulators/FPGA prototypes.
• Verify compute datapaths against bit-accurate models and run ML kernels.
• Apply formal verification and triage regression failures across platforms.

Conhecimentos

SystemVerilog/UVM

C/C++

Python scripting

RTL debugging

Emulation/FPGA

SVA

AI accelerator basics

Formação

Bachelor's or Master's in Electrical/Computer Engineering or CS

Ferramentas

SystemVerilog

UVM

Emulation platforms

FPGA prototyping

ISA simulators

Descrição da vaga

Join our hardware team as AI Accelerator Design verification engineer verifying the state of the art AI chip, with hands-on ownership of verification environments from test plan through coverage closure and SI bring-up.

What you'll do

• Develop verification plans for AI accelerator blocks: tensor processing, fabric / network-on-chip, and SoC flows
• Write and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models for your assigned block or subsystem
• Build emulation-friendly testbenches: synthesizable, transactor-based environments that run the same tests in simulation and on emulators or FPGA prototypes
• Use agentic AI tools across the verification workflow: generating test plans from specifications, writing and reviewing testbench code, triaging regression failures, root-causing bugs, and analyzing coverage. Review and validate everything the agents produce
• Verify numerical correctness of compute datapaths (FP*) against bit-accurate golden models
• Run real ML kernels and random programs on the RTL, co-simulated against an ISA/architectural reference model
• Define, implement, and close functional and code coverage goals, analyzing holes and driving them to closure
• Debug failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs
• Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency
• Run and maintain regressions across simulation, emulation, and FPGA platforms, and track bug trends and verification progress metrics
• Partner with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals
• Participate in microarchitecture, RTL, and verification reviews, and write technical documentation

What we're looking for

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Strong foundation in AI accelerator and computer architecture and digital design, with solid understanding of following:
• Tensor cores and SIMT / SIMD / vector processing
• Floating-point / computer arithmetic, including reduced-precision formats
• On-chip memories, scratchpads, and DMA engines
• Cache hierarchy, memory systems, and HBM/DRAM interfaces
• Network-on-chip and on-chip interconnects
• Dataflow, scheduling, and synchronization across many compute cores
• Working knowledge of modern AI accelerator flows and ISAs, including familiarity with ISA simulators or reference models
• Proficiency in System Verilog, C/C++, assembly
• Familiarity with emulation-friendly verification (synthesizable testbenches, transactors) is a plus
• Hands-on experience using agentic AI tools across the engineering workflow: delegating multi-step tasks to agents, writing clear instructions and context, and checking their results critically
• Scripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust
• Exposure to ML frameworks or workloads (PyTorch, TensorFlow, or ONNX) is a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)