Senior AI Accelerator Verification Engineer

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Equity compensation

Competitive base salary

Job summary

Velaura AI, Inc. is seeking a Design Verification Engineer to verify its AI acceleration units, focusing on matrix and vector compute engines and their numerical correctness.

You will work with architects, RTL and software teams to create detailed test plans, build portable verification environments in SystemVerilog/UVM, and develop reference models in C/C++/Python. The role demands strong ownership, performance awareness, and the ability to validate precision and throughput under LLM/vision

Qualifications

• 8+ years verifying high performance compute or complex digital designs.
• High level understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience building or using reference models in C, C++ or Python.
• Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
• Experience owning a block or unit of a design independently from test plan through coverage closure.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.

Responsibilities

• Own verification of Velaura's AI acceleration units including matrix and vector compute engines.
• Develop test and coverage plans with architect input to define numerical correctness.
• Build verification environments using SystemVerilog, UVM, C and C++, with portable stimulus and coverage.
• Develop reference models for GEMM and GEMV and compare against hardware results.
• Verify data flow: operand staging, tiling, accumulation and writeback.
• Assess precision, rounding and quantization per architecture spec.
• Evaluate throughput, latency, and power metrics against targets on workloads.
• Execute regressions and track progress with bugs and coverage metrics.

Skills

8+ yrs experience

SystemVerilog/UVM

C/C++

Python

Numerical formats FP16/BF16/FP8/INT8

Ownership of test plan to coverage

Education

BS or higher in Computer Engineering, Electrical Engineering or Computer Science

Tools

SystemVerilog

UVM

C/C++

Python

Job description

Velaura AI, Inc. is seeking a Design Verification Engineer to verify its AI acceleration units, focusing on matrix and vector compute engines and their numerical correctness.

You will work with architects, RTL and software teams to create detailed test plans, build portable verification environments in SystemVerilog/UVM, and develop reference models in C/C++/Python. The role demands strong ownership, performance awareness, and the ability to validate precision and throughput under LLM/vision