AI Accelerator Architect for Ultra-Efficient LLM Inference

Normal Computing Corporation; Palo Alto (CA); On-site; USD 220,000 - 360,000; Full time

Job summary

Normal Computing is building a new breed of AI accelerator hardware to boost energy efficiency for large language model and diffusion workloads. The Hardware ASIC Architect will define silicon and system microarchitecture for an unconventional compute platform, aiming for a 100–1000x leap in energy efficiency over traditional chips.

You will lead hardware/software co-design, translate transformer and diffusion workloads into custom tiles and memory hierarchies, and collaborate with RTL,

Qualifications

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
• Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic.
• Fluency moving between algorithm-level analysis and hardware specification. Translate workload into datapath widths, pipeline stages, and area/power estimates.
• Experience with simulation-driven architecture using cycle-accurate or analytical models.
• Familiarity with quantization and reduced-precision approaches for inference and their hardware implications.
• Experience writing microarchitecture specifications and working closely with RTL engineers.
• Proficiency in Python or C++ for performance modeling and familiarity with SystemVerilog or RTL.
• Comfort operating in an environment where architecture is actively being discovered alongside the work.

Responsibilities

• Define the architecture and microarchitecture of novel AI accelerator compute blocks.
• Translate workload analysis into hardware specifications for RTL.
• Defend full-stack PPA tradeoffs across algorithm, memory, interconnect and physical design.
• Partner with compiler lead on ISA co-design and ensure alignment.
• Direct block-level pre-silicon validation and coordinate with FPGA design engineers.
• Stay current with AI accelerator research and articulate distinguishing advantages.

Skills

AI accelerator architecture

Digital system design

Python or C++

SystemVerilog/RTL

Simulation-driven development

Quantization / low-precision

Workload-to-hardware translation

Problem solving in hardware

Education

B.E./B.S. in Electrical/Computer Engineering or Computer Science

PhD welcome but not required

Tools

SystemVerilog

RTL

Cycle-accurate simulators

Job description

Normal Computing is building a new breed of AI accelerator hardware to boost energy efficiency for large language model and diffusion workloads. The Hardware ASIC Architect will define silicon and system microarchitecture for an unconventional compute platform, aiming for a 100–1000x leap in energy efficiency over traditional chips.

You will lead hardware/software co-design, translate transformer and diffusion workloads into custom tiles and memory hierarchies, and collaborate with RTL,